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1.1. Installing and Licensing Intel® FPGA IP Cores
1.2. Design Flow
1.3. Upgrading IP Cores
1.4. Floating-Point IP Cores General Features
1.5. IEEE-754 Standard for Floating-Point Arithmetic
1.6. Non-IEEE-754 Standard Format
1.7. Floating-Points IP Cores Output Latency
1.8. VHDL Component Declaration
1.9. VHDL LIBRARY-USE Declaration
3.1. Floating Point Functions IP Features
3.2. Floating Point Functions IP Output Latency
3.3. Floating Point Functions IP Target Frequency
3.4. Floating Point Functions IP Combined Target
3.5. Floating Point Functions IP Reset and Latency
3.6. Floating Point Functions IP Signals
3.7. Floating-Point Functions IP Parameters
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1.5.2. Special Case Numbers
The following table lists the special case numbers defined by the IEEE-754 standard and the data bit representations.
Meaning | Sign Field | Exponent Field | Mantissa Field |
---|---|---|---|
Zero | Don’t care | All 0’s | All 0’s |
Positive Denormalized | 0 | All 0’s | Non-zero |
Negative Denormalized | 1 | All 0’s | Non-zero |
Positive Infinity | 0 | All 1’s | All 0’s |
Negative Infinity | 1 | All 1’s | All 0’s |
Not-a-Number (NaN) | Don’t care | All 1’s | Non-zero |