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1.1. Installing and Licensing Intel® FPGA IP Cores
1.2. Design Flow
1.3. Upgrading IP Cores
1.4. Floating-Point IP Cores General Features
1.5. IEEE-754 Standard for Floating-Point Arithmetic
1.6. Non-IEEE-754 Standard Format
1.7. Floating-Points IP Cores Output Latency
1.8. VHDL Component Declaration
1.9. VHDL LIBRARY-USE Declaration
3.1. Floating Point Functions IP Features
3.2. Floating Point Functions IP Output Latency
3.3. Floating Point Functions IP Target Frequency
3.4. Floating Point Functions IP Combined Target
3.5. Floating Point Functions IP Reset and Latency
3.6. Floating Point Functions IP Signals
3.7. Floating-Point Functions IP Parameters
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1.5.1.2. Double-Precision Format
The double-precision format contains the following binary patterns:
- The MSB holds the sign bit.
- The next 11 bits hold the exponent bits.
- 52 LSBs hold the mantissa.
The total width of a floating-point number in the double-precision format is 64 bits. The bias for the double-precision format is 1023.
Figure 11. Double-Precision RepresentationThis figure shows a double-precision representation.