Floating-Point Intel® FPGA IP User Guide

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ID 683750
Date 8/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. About Floating-Point Intel® FPGA IP 2. Floating Point Custom Accumulator Intel® FPGA IP 3. Floating Point Functions IP 4. Floating-Point IP Cores User Guide Document Archives 5. Document Revision History for the Floating-Point Intel® FPGA IPUser Guide
1. About Floating-Point Intel® FPGA IP x
1.1. Installing and Licensing Intel® FPGA IP Cores 1.2. Design Flow 1.3. Upgrading IP Cores 1.4. Floating-Point IP Cores General Features 1.5. IEEE-754 Standard for Floating-Point Arithmetic 1.6. Non-IEEE-754 Standard Format 1.7. Floating-Points IP Cores Output Latency 1.8. VHDL Component Declaration 1.9. VHDL LIBRARY-USE Declaration
1.2. Design Flow x
1.2.1. IP Catalog and Parameter Editor 1.2.2. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition)
1.2.1. IP Catalog and Parameter Editor x
1.2.1.1. The Parameter Editor
1.2.2. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) x
1.2.2.1. IP Core Generation Output ( Quartus® Prime Pro Edition)
1.3. Upgrading IP Cores x
1.3.1. Migrating IP Cores to a Different Device
1.5. IEEE-754 Standard for Floating-Point Arithmetic x
1.5.1. Floating-Point Formats 1.5.2. Special Case Numbers 1.5.3. Rounding
1.5.1. Floating-Point Formats x
1.5.1.1. Single-Precision Format 1.5.1.2. Double-Precision Format 1.5.1.3. Single-Extended Precision Format
2. Floating Point Custom Accumulator Intel® FPGA IP x
2.1. Floating Point Custom Accumulator Intel® FPGA IP Features 2.2. Floating Point Custom Accumulator Intel® FPGA IP Output Latency 2.3. Floating Point Custom Accumulator Intel® FPGA IP Signals 2.4. Floating Point Custom Accumulator Intel® FPGA IP Parameters
3. Floating Point Functions IP x
3.1. Floating Point Functions IP Features 3.2. Floating Point Functions IP Output Latency 3.3. Floating Point Functions IP Target Frequency 3.4. Floating Point Functions IP Combined Target 3.5. Floating Point Functions IP Reset and Latency 3.6. Floating Point Functions IP Signals 3.7. Floating-Point Functions IP Parameters
1. About Floating-Point Intel® FPGA IP
2. Floating Point Custom Accumulator Intel® FPGA IP
3. Floating Point Functions IP
4. Floating-Point IP Cores User Guide Document Archives
5. Document Revision History for the Floating-Point Intel® FPGA IPUser Guide

2.3. Floating Point Custom Accumulator Intel® FPGA IP Signals

Figure 14. Floating Point Custom Accumulator Intel® FPGA IP
Table 7.  Floating Point Custom Accumulator Intel® FPGA IP Input Ports
Port Name Required Description
clk Yes All input signals, unless otherwise explicitly stated, must be synchronous to this clock
areset Yes

Active-high reset. Asynchronous for Arria 10 and Cyclone 10 GX devices; synchronous for Agilex devices.

For asynchronous reset, deassert the reset signal synchronously to the input clock to avoid metastability issues.

For synchronous reset, minimizing resets, whenever functionally safe, gives better performance. Synchronous reset may connect to all of the design, some of the design, or none of the design at all.

Valid data is available at the the output L cycles after deasserting reset where L is the latency of the IP.

en No Global enable signal. This port is optional.
x Yes Data input port.
n Yes Boolean port which signals the beginning of a new data set to be accumulated. This should go high together with the first element in the new data set and should go low the next cycle. The data sets may be of variable length and a new data set may be started at any time. The accumulation result for an input is available after the reported latency.
Table 8.  Floating Point Custom Accumulator Intel® FPGA IP Output Ports
Port Name Required Description
r Yes The running value of the accumulation.
xo Yes The overflow flag for port x. The signal goes high when the exponent of the input x is larger than maxMSBX (refer to Floating Point Custom Accumulator Intel FPGA IP Parameters). The signal remains high for the entire data set. This flag invalidates port r. You should consider increasing maxMSBX. This flag also indicates infinity and NaN.
xu Yes The underflow flag for port x. The signal goes high when the exponent of the input x is smaller than LSBA (refer to Floating Point Custom Accumulator Intel FPGA IP Parameters). The signal remains high for the entire data set. This flag does not invalidate port r. You should consider lowering LSBA.
ao Yes The overflow flag for Accumulator. The signal goes high when the exponent of the accumulated value is larger than MSBA (refer to Floating Point Custom Accumulator Intel FPGA IP Parameters). The signal remains high for the entire data set. This flag invalidates port r. You should consider increasing MSBA.
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