Floating-Point Intel® FPGA IP User Guide

Download PDF
ID 683750
Date 8/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. About Floating-Point Intel® FPGA IP 2. Floating Point Custom Accumulator Intel® FPGA IP 3. Floating Point Functions IP 4. Floating-Point IP Cores User Guide Document Archives 5. Document Revision History for the Floating-Point Intel® FPGA IPUser Guide
1. About Floating-Point Intel® FPGA IP x
1.1. Installing and Licensing Intel® FPGA IP Cores 1.2. Design Flow 1.3. Upgrading IP Cores 1.4. Floating-Point IP Cores General Features 1.5. IEEE-754 Standard for Floating-Point Arithmetic 1.6. Non-IEEE-754 Standard Format 1.7. Floating-Points IP Cores Output Latency 1.8. VHDL Component Declaration 1.9. VHDL LIBRARY-USE Declaration
1.2. Design Flow x
1.2.1. IP Catalog and Parameter Editor 1.2.2. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition)
1.2.1. IP Catalog and Parameter Editor x
1.2.1.1. The Parameter Editor
1.2.2. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) x
1.2.2.1. IP Core Generation Output ( Quartus® Prime Pro Edition)
1.3. Upgrading IP Cores x
1.3.1. Migrating IP Cores to a Different Device
1.5. IEEE-754 Standard for Floating-Point Arithmetic x
1.5.1. Floating-Point Formats 1.5.2. Special Case Numbers 1.5.3. Rounding
1.5.1. Floating-Point Formats x
1.5.1.1. Single-Precision Format 1.5.1.2. Double-Precision Format 1.5.1.3. Single-Extended Precision Format
2. Floating Point Custom Accumulator Intel® FPGA IP x
2.1. Floating Point Custom Accumulator Intel® FPGA IP Features 2.2. Floating Point Custom Accumulator Intel® FPGA IP Output Latency 2.3. Floating Point Custom Accumulator Intel® FPGA IP Signals 2.4. Floating Point Custom Accumulator Intel® FPGA IP Parameters
3. Floating Point Functions IP x
3.1. Floating Point Functions IP Features 3.2. Floating Point Functions IP Output Latency 3.3. Floating Point Functions IP Target Frequency 3.4. Floating Point Functions IP Combined Target 3.5. Floating Point Functions IP Reset and Latency 3.6. Floating Point Functions IP Signals 3.7. Floating-Point Functions IP Parameters
1. About Floating-Point Intel® FPGA IP
2. Floating Point Custom Accumulator Intel® FPGA IP
3. Floating Point Functions IP
4. Floating-Point IP Cores User Guide Document Archives
5. Document Revision History for the Floating-Point Intel® FPGA IPUser Guide

1.2.2. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition)

You configure Intel® FPGA IP in the Quartus® Prime parameter editor. Double-click any component in the IP Catalog to launch the parameter editor. The parameter editor allows you to define a custom variation of the IP. The parameter editor generates the IP variation synthesis and optional simulation files, and adds the .ip file representing the variation to your project automatically.

To locate, instantiate, and customize an IP in the parameter editor:

  1. Create or open an Quartus® Prime project (.qpf) to contain the instantiated IP variation.
  2. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP to customize. To locate a specific component, type some or all of the component’s name in the IP Catalog search box. The New IP Variation window appears.
  3. Specify a top-level name for your custom IP variation. Do not include spaces in IP variation names or paths. The parameter editor saves the IP variation settings in a file named <your_ip> .ip. Click OK. The parameter editor appears.
    Figure 4. IP Parameter Editor ( Quartus® Prime Pro Edition)


  4. Set the parameter values in the parameter editor and view the block diagram for the component. The Parameterization Messages tab at the bottom displays any errors in IP parameters:
    • Optionally, select preset parameter values if provided for your IP. Presets specify initial parameter values for specific applications.
    • Specify parameters defining the IP functionality, port configurations, and device-specific features.
    • Specify options for processing the IP files in other EDA tools.
    Note: Refer to your IP user guide for information about specific IP parameters.
  5. Click Generate HDL. The Generation dialog box appears.
  6. Specify output file generation options, and then click Generate. The synthesis and simulation files generate according to your specifications.
  7. To generate a simulation testbench, click Generate > Generate Testbench System. Specify testbench generation options, and then click Generate.
  8. To generate an HDL instantiation template that you can copy and paste into your text editor, click Generate > Show Instantiation Template.
  9. Click Finish. Click Yes if prompted to add files representing the IP variation to your project.
  10. After generating and instantiating your IP variation, make appropriate pin assignments to connect ports.
    Note: Some IPs generate different HDL implementations according to the IP parameters. The underlying RTL of these IP contains a unique hash code that prevents module name collisions between different variations of the IP. This unique code remains consistent, given the same IP settings and software version during IP generation. This unique code can change if you edit the IP's parameters or upgrade the IP version. To avoid dependency on these unique codes in your simulation environment, refer to Generating a Combined Simulator Setup Script.

Section Content
IP Core Generation Output ( Quartus Prime Pro Edition)

Level Two Title