Floating-Point Intel® FPGA IP User Guide

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ID 683750
Date 8/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. About Floating-Point Intel® FPGA IP 2. Floating Point Custom Accumulator Intel® FPGA IP 3. Floating Point Functions IP 4. Floating-Point IP Cores User Guide Document Archives 5. Document Revision History for the Floating-Point Intel® FPGA IPUser Guide
1. About Floating-Point Intel® FPGA IP x
1.1. Installing and Licensing Intel® FPGA IP Cores 1.2. Design Flow 1.3. Upgrading IP Cores 1.4. Floating-Point IP Cores General Features 1.5. IEEE-754 Standard for Floating-Point Arithmetic 1.6. Non-IEEE-754 Standard Format 1.7. Floating-Points IP Cores Output Latency 1.8. VHDL Component Declaration 1.9. VHDL LIBRARY-USE Declaration
1.2. Design Flow x
1.2.1. IP Catalog and Parameter Editor 1.2.2. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition)
1.2.1. IP Catalog and Parameter Editor x
1.2.1.1. The Parameter Editor
1.2.2. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) x
1.2.2.1. IP Core Generation Output ( Quartus® Prime Pro Edition)
1.3. Upgrading IP Cores x
1.3.1. Migrating IP Cores to a Different Device
1.5. IEEE-754 Standard for Floating-Point Arithmetic x
1.5.1. Floating-Point Formats 1.5.2. Special Case Numbers 1.5.3. Rounding
1.5.1. Floating-Point Formats x
1.5.1.1. Single-Precision Format 1.5.1.2. Double-Precision Format 1.5.1.3. Single-Extended Precision Format
2. Floating Point Custom Accumulator Intel® FPGA IP x
2.1. Floating Point Custom Accumulator Intel® FPGA IP Features 2.2. Floating Point Custom Accumulator Intel® FPGA IP Output Latency 2.3. Floating Point Custom Accumulator Intel® FPGA IP Signals 2.4. Floating Point Custom Accumulator Intel® FPGA IP Parameters
3. Floating Point Functions IP x
3.1. Floating Point Functions IP Features 3.2. Floating Point Functions IP Output Latency 3.3. Floating Point Functions IP Target Frequency 3.4. Floating Point Functions IP Combined Target 3.5. Floating Point Functions IP Reset and Latency 3.6. Floating Point Functions IP Signals 3.7. Floating-Point Functions IP Parameters
1. About Floating-Point Intel® FPGA IP
2. Floating Point Custom Accumulator Intel® FPGA IP
3. Floating Point Functions IP
4. Floating-Point IP Cores User Guide Document Archives
5. Document Revision History for the Floating-Point Intel® FPGA IPUser Guide

5. Document Revision History for the Floating-Point Intel® FPGA IPUser Guide

Document Version Quartus® Prime Version Changes
2024.10.15 24.2 Added more description to areset.
2024.08.30 24.2
  • Removed all Quartus® Prime Standard Edition IPs.
  • Added Floating Point Functions Reset and Latency
2024.07.31 23.1 Updated Table: List of Functions Supported by FP_FUNCTIONS Intel® FPGA IP or Floating Point Functions Intel® FPGA IP
2023.05.03 23.1
  • Updated the product family name to "Intel Agilex 7."
  • Corrected title: ALTFP_ADD_SUB Design Example: Understanding the Simulation Results
2022.10.27 20.1 Updated VHDL Component Declaration to

The VHDL component declaration is located in eda\fv_lib\vhdl\megafunctions\altera_mf_components.vhd

2021.09.13 20.1 Updated List of Functions Supported by FP_FUNCTIONS Intel® FPGA IP or Floating Point Functions Intel® FPGA IP
2021.03.12 20.1 Updated the supported device for FP_FUNCTIONS Intel FPGA IP to include Arria® 10 devices in Table: IP Cores Available in Quartus® Prime Standard Edition Software.
2020.06.22 20.1
  • Added IP Cores Available in Quartus® Prime Standard Edition Software and IP Cores Available in Quartus® Prime Pro Edition Software tables.
  • Removed information about the ALTERA_FP_MATRIX_INV and ALTERA_FP_MATRIX_MULT_IP cores. These cores are no longer supported in versions 20.1 and later.
  • Rebranded the entire document as per Intel standards.
  • Renamed ALTERA_FP_ACC_CUSTOM IP Core to FP_ACC_CUSTOM Intel FPGA IP or Floating Point Custom Accumulator Intel FPGA IP.
  • Renamed ALTERA_FP_FUNCTIONS IP Core to FP_FUNCTIONS Intel FPGA IP or Floating Point Functions Intel FPGA IP.
  • Added Floating Point Custom Accumulator Intel® FPGA IP Release Information and Floating Point Functions Intel® FPGA IP Release Information tables.
  • Updated the VHDL LIBRARY-USE Declaration topic to correct the VHDL Library declaration example from USE altera_mf_altera_mf_components.all; to USE altera_mf.altera_mf_components.all;.
Date Document Version Changes Made
December 2016 2016.12.09
  • Added simple description about the IP core on each introduction page.
  • Added descriptions for each function supported by ALTERA_FP_FUNCTIONS IP core.
  • Clarified that ALTERA_FP_FUNCTIONS IP core replaces all ALTFP IP cores in Arria 10 devices.
  • Added new parameters in ALTERA_FP_FUNCTIONS Parameter: Functionality Tab table.
  • Clarified the functionality of en signal for ALTERA_FP_FUNCTIONS.
July 2015 2015.07.30
  • Updated link to Floating-Point IP Cores Design Examples.
  • Updated Memory Blocks numbers in ALTERA_FP_MATRIX_MULT Resource Utilization and Performance for the Arria 10 and Stratix V Devices table.
  • Added notes on default settings for WIDTH_INT and WIDTH_DATA.
December 2014 2014.12.19
  • Remove all references to the complex mode in ALTFP_MATRIX_MULTIPLY.
  • Updated ALTERA_FP_MATRIX_MULT and ALTERA_FP_FUNCTIONS sections.
November 2013 7.0
  • Added “ALTERA_FP_FUNCTIONS” on page 3–1.
  • Added “ALTERA_FP_ACC_CUSTOM” on page 2–1.
  • Updated Table 1–1 on page 1–1 to list ALTERA_FP_FUNCTIONS and ALTERA_FP_ACC_CUSTOM.
  • Updated the “ALTFP_MATRIX_INV” on page 17–1 section to include 4 x 4 and 6 x 6 dimensions.
  • Updated “Rounding” on page 1–4 to clarify that the code for round-to-nearest-even mode is TO_NEAREST.
  • Removed Design Example section for “ALTFP_MATRIX_MULT” on page 18–1.
  • Removed device family support for HardCopy III, HardCopy IV, Stratix II, and Stratix II GX devices from “Device Family Support” on page 1–2.
November 2011 6.0 Updated “General Features” on page 1–2.
May 2011 5.0 Added “ALTFP_ATAN” on page 12–1.
January 2011 4.0 Added “ALTFP_SINCOS” on page 13–1.
July 2010 3.0
  • Updated architecture information for the following sections:

    ALTFP_MATRIX_MULT

    ALTFP_MATRIX_INV.

  • Added specification information in all sections.
November 2009 2.0
  • Updated resource utilization information for the following sections:

    ALTFP_ADD_SUB

    ALTFP_DIV

    ALTFP_MULT

    ALTFP_SQRT

    ALTFP_EXP

    ALTFP_INV

    ALTFP_INV_SQRT

    ALTFP_LOG

    ALTFP_COMPARE

    ALTFP_CONVERT

    ALTFP_MATRIX_MULT

  • Added the ALTFP_MATRIX_INV section.
  • Updated the Ports and Parameters section for all floating-point megafunctions.
March 2009 1.0 Initial release.
Level Two Title