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1.1. Installing and Licensing Intel® FPGA IP Cores
1.2. Design Flow
1.3. Upgrading IP Cores
1.4. Floating-Point IP Cores General Features
1.5. IEEE-754 Standard for Floating-Point Arithmetic
1.6. Non-IEEE-754 Standard Format
1.7. Floating-Points IP Cores Output Latency
1.8. VHDL Component Declaration
1.9. VHDL LIBRARY-USE Declaration
3.1. Floating Point Functions IP Features
3.2. Floating Point Functions IP Output Latency
3.3. Floating Point Functions IP Target Frequency
3.4. Floating Point Functions IP Combined Target
3.5. Floating Point Functions IP Reset and Latency
3.6. Floating Point Functions IP Signals
3.7. Floating-Point Functions IP Parameters
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1.4. Floating-Point IP Cores General Features
All Intel FPGA floating-point IPs offer the following features:
- Support for floating-point formats.
- Input support for not-a-number (NaN), infinity, zero, and normal numbers.
- Optional asynchronous input ports including asynchronous clear (aclr) and clock enable (clk_en).
- Support for round to nearest with tie breaking to even.
- Compute results of any mathematical operations according to the IEEE-754 standard compliance with a maximum of 1 unit in the last place (u.l.p.) error. This assumption is applied to all floating-point IPs.
Intel FPGA floating-point IPs do not support denormal number inputs. If the input is a denormal value, the IP forces the value to zero and treats the value as a zero before going through any operation.
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