Floating-Point Intel® FPGA IP User Guide

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ID 683750
Date 8/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. About Floating-Point Intel® FPGA IP 2. Floating Point Custom Accumulator Intel® FPGA IP 3. Floating Point Functions IP 4. Floating-Point IP Cores User Guide Document Archives 5. Document Revision History for the Floating-Point Intel® FPGA IPUser Guide
1. About Floating-Point Intel® FPGA IP x
1.1. Installing and Licensing Intel® FPGA IP Cores 1.2. Design Flow 1.3. Upgrading IP Cores 1.4. Floating-Point IP Cores General Features 1.5. IEEE-754 Standard for Floating-Point Arithmetic 1.6. Non-IEEE-754 Standard Format 1.7. Floating-Points IP Cores Output Latency 1.8. VHDL Component Declaration 1.9. VHDL LIBRARY-USE Declaration
1.2. Design Flow x
1.2.1. IP Catalog and Parameter Editor 1.2.2. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition)
1.2.1. IP Catalog and Parameter Editor x
1.2.1.1. The Parameter Editor
1.2.2. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) x
1.2.2.1. IP Core Generation Output ( Quartus® Prime Pro Edition)
1.3. Upgrading IP Cores x
1.3.1. Migrating IP Cores to a Different Device
1.5. IEEE-754 Standard for Floating-Point Arithmetic x
1.5.1. Floating-Point Formats 1.5.2. Special Case Numbers 1.5.3. Rounding
1.5.1. Floating-Point Formats x
1.5.1.1. Single-Precision Format 1.5.1.2. Double-Precision Format 1.5.1.3. Single-Extended Precision Format
2. Floating Point Custom Accumulator Intel® FPGA IP x
2.1. Floating Point Custom Accumulator Intel® FPGA IP Features 2.2. Floating Point Custom Accumulator Intel® FPGA IP Output Latency 2.3. Floating Point Custom Accumulator Intel® FPGA IP Signals 2.4. Floating Point Custom Accumulator Intel® FPGA IP Parameters
3. Floating Point Functions IP x
3.1. Floating Point Functions IP Features 3.2. Floating Point Functions IP Output Latency 3.3. Floating Point Functions IP Target Frequency 3.4. Floating Point Functions IP Combined Target 3.5. Floating Point Functions IP Reset and Latency 3.6. Floating Point Functions IP Signals 3.7. Floating-Point Functions IP Parameters
1. About Floating-Point Intel® FPGA IP
2. Floating Point Custom Accumulator Intel® FPGA IP
3. Floating Point Functions IP
4. Floating-Point IP Cores User Guide Document Archives
5. Document Revision History for the Floating-Point Intel® FPGA IPUser Guide

3.7. Floating-Point Functions IP Parameters

These tables list the Floating-Point Functions Intel® FPGA IP parameters.
Table 14.  Floating-Point Functions Intel® FPGA IP Parameters: Functionality Tab
Parameter Values Descriptions
Function
Family
  • All
  • Arithmetic
  • Comparisons
  • Conversions
  • Exp/Log/Pow
  • Roots
  • Trigonometry
 Allows you to choose which functions to be displayed in the Function Name Parameter list. The default value is All.
Name
  • Add
  • Subtract
  • Add/Sub
  • Multiply
  • Divide
  • Reciprocal
  • Absolute
  • Scalar Product
  • Multiply Accumulate
  • Accumulate
  • Multiply Add
  • Complex Multiply
  • Sin
  • Cos
  • Tan
  • Arcsin
  • Arccos
  • Arctan
  • Arctan2
  • Exponent
  • Exponent base 2
  • Exponent base 10
  • Log
  • Log2
  • Log10
  • Log(1+x)
  • Power
  • Square Root
  • Reciprocal Square Root
  • Cube Root
  • 3D Hypotenuse
  • Minimum
  • Maximum
  • Less Than
  • Less Than or Equal
  • Equal
  • Not Equal
  • Greater Than
  • Greater Than or Equal
  • Fixed to Floating Point
  • Floating Point to Fixed
  • Floating to Floating Point
 Allows you to choose your desired function.
Note: This parameter only displays the options you have selected from the Family Parameter.
Use Select Signal On or off Select this option to generate a Select signal.

Use the Select signal to choose the option to use both addition and subtraction functions or either one of the functions.

Represent angle as multiple of Pi On or off Select this option to represent angles as multiple of Pi.
Note: Not available for Arctan2 function.
Inputs are within range -2pi to +2pi On or off Select this option to disable range reduction.
Note: Only available for Sin and Cos function.
Floating Point Data
Format

Single

Double

Custom

 Allows you to choose the floating point format of the data values. The default value is single.
Exponent 5 to 11 Allows you to specify the width of the exponent. This parameter is only available when the Format parameter is set to custom. The default value is 8.
Mantissa 10 to 52 Allows you to specify the width of the mantissa. This parameter is only available when the Format parameter is set to custom. The default value is 23.
Input Vector Dimension Integer Provide the desired the number of inputs to compute the vector dimension.
Input Format

Single

Double

Custom

 Allows you to choose the floating point format of the input data values. The default value is single.
Note: Only available for Floating to Floating Point function.
Input Exponent Integer Allows you to specify the width of the input exponent. This parameter is only available when the Format parameter is set to custom. The default value is 8.
Note: Only available for Floating to Floating Point function.
Input Mantissa Integer Allows you to specify the width of the mantissa. This parameter is only available when the Format parameter is set to custom. The default value is 23.
Note: Only available for Floating to Floating Point function.
Output Format

Single

Double

Custom

 Allows you to choose the floating point format of the output data values. The default value is single.
Output Exponent Integer Allows you to specify the width of the output exponent. This parameter is only available when the Format parameter is set to custom. The default value is 8.
Note: Only available for Floating to Floating Point function.
Output Mantissa Integer Allows you to specify the width of the mantissa. This parameter is only available when the Format parameter is set to custom. The default value is 23.
Note: Only available for Floating to Floating Point function.
Fixed Point Data
Width 16 to 128 The bit width of the fixed point data port. This parameter is only available when the Name parameter is set to Fixed to Floating Point. The default value is 32.
Fraction -128 to 128 The bit width of the fraction. This parameter is only available when the Name parameter is set to Fixed to Floating Point.
Sign

Signed

Unsigned

 Choose if the fixed point data is signed or unsigned. This parameter is only available when the Name parameter is set to Convert. The default value is signed.
Rounding
Mode nearest with tie breaking to even The rounding mode.
Relax rounding to round up or down to reduce resource usage — Choose if the nearest rounding mode should be relaxed to faithful rounding, where the result may be rounded up or down, to reduce resource usage. Only available for arithmetic functions
Ports
Generate Enable Port — Choose if the FP_FUNCTIONS Intel® FPGA IP core should have an enable signal.
Table 15.  Floating-Point Functions Intel® FPGA IP Parameters: Performance Tab
Parameter Values Descriptions
Target
Goal
  • Frequency
  • Latency
  • Combined
  • Manually Specify DSP Registers
 If the Goal is the frequency, then the Target is the desired frequency in MHz. This, together with the target device family, determines the amount of pipelining. If the Goal is Combined then two Targets are displayed, one is the desired frequency in MHz, one is the target latency in cycles. When you set the Goal parameter to frequency, the default value is 200 MHz When you set the Goal parameter to latency, the default value is 2.

If the Goal is Latency, then the Target is the desired latency. The report generates the achievable latency if it can't meet target latency.

If the Goal is set to Manually Specify DSP Registers, you can manually select the register and function subblocks within the DSP IP core.

Target Any Positive Integer Specify your target frequency and latency.
Report
Latency on Arria 10 is <x> cycles — This report shows the latency of the function.
Resource Estimates:
  • Multiplies
  • LUTs
  • Memory Bits
  • Memory Blocks
— This report shows the number of multipliers, LUTs, memory bits, and memory blocks utilized by the IP core.
Check Performance — Click this to check if the design can achieve the target latency.
Note: Only available when Goal is set to Latency.
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