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1.1. Installing and Licensing Intel® FPGA IP Cores
1.2. Design Flow
1.3. Upgrading IP Cores
1.4. Floating-Point IP Cores General Features
1.5. IEEE-754 Standard for Floating-Point Arithmetic
1.6. Non-IEEE-754 Standard Format
1.7. Floating-Points IP Cores Output Latency
1.8. VHDL Component Declaration
1.9. VHDL LIBRARY-USE Declaration
3.1. Floating Point Functions IP Features
3.2. Floating Point Functions IP Output Latency
3.3. Floating Point Functions IP Target Frequency
3.4. Floating Point Functions IP Combined Target
3.5. Floating Point Functions IP Reset and Latency
3.6. Floating Point Functions IP Signals
3.7. Floating-Point Functions IP Parameters
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3.6. Floating Point Functions IP Signals
Figure 15. Floating Point Functions Intel® FPGA IP Signals
Port Name | Required | Description |
---|---|---|
clk | Yes | All input signals must be synchronous to this clock. |
areset | Yes | Asynchronous active-high reset. Deassert this signal synchronously to the input clock to avoid metastability issues. |
en | No | Optional port. Allow calculation to take place when asserted. When deasserted, no operation will take place and the outputs are unchanged. |
a | Yes | Data input signal. |
b | Yes | Data input signal (where applicable). |
s | Yes | Select port for Add/Sub function. |
c | Yes | Data port for integer exponent port for LDExp function. |
Port Name | Required | Description |
---|---|---|
q | Yes | Data output signal. |