Floating-Point Intel® FPGA IP User Guide

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ID 683750
Date 8/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. About Floating-Point Intel® FPGA IP 2. Floating Point Custom Accumulator Intel® FPGA IP 3. Floating Point Functions IP 4. Floating-Point IP Cores User Guide Document Archives 5. Document Revision History for the Floating-Point Intel® FPGA IPUser Guide
1. About Floating-Point Intel® FPGA IP x
1.1. Installing and Licensing Intel® FPGA IP Cores 1.2. Design Flow 1.3. Upgrading IP Cores 1.4. Floating-Point IP Cores General Features 1.5. IEEE-754 Standard for Floating-Point Arithmetic 1.6. Non-IEEE-754 Standard Format 1.7. Floating-Points IP Cores Output Latency 1.8. VHDL Component Declaration 1.9. VHDL LIBRARY-USE Declaration
1.2. Design Flow x
1.2.1. IP Catalog and Parameter Editor 1.2.2. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition)
1.2.1. IP Catalog and Parameter Editor x
1.2.1.1. The Parameter Editor
1.2.2. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) x
1.2.2.1. IP Core Generation Output ( Quartus® Prime Pro Edition)
1.3. Upgrading IP Cores x
1.3.1. Migrating IP Cores to a Different Device
1.5. IEEE-754 Standard for Floating-Point Arithmetic x
1.5.1. Floating-Point Formats 1.5.2. Special Case Numbers 1.5.3. Rounding
1.5.1. Floating-Point Formats x
1.5.1.1. Single-Precision Format 1.5.1.2. Double-Precision Format 1.5.1.3. Single-Extended Precision Format
2. Floating Point Custom Accumulator Intel® FPGA IP x
2.1. Floating Point Custom Accumulator Intel® FPGA IP Features 2.2. Floating Point Custom Accumulator Intel® FPGA IP Output Latency 2.3. Floating Point Custom Accumulator Intel® FPGA IP Signals 2.4. Floating Point Custom Accumulator Intel® FPGA IP Parameters
3. Floating Point Functions IP x
3.1. Floating Point Functions IP Features 3.2. Floating Point Functions IP Output Latency 3.3. Floating Point Functions IP Target Frequency 3.4. Floating Point Functions IP Combined Target 3.5. Floating Point Functions IP Reset and Latency 3.6. Floating Point Functions IP Signals 3.7. Floating-Point Functions IP Parameters
1. About Floating-Point Intel® FPGA IP
2. Floating Point Custom Accumulator Intel® FPGA IP
3. Floating Point Functions IP
4. Floating-Point IP Cores User Guide Document Archives
5. Document Revision History for the Floating-Point Intel® FPGA IPUser Guide

2.4. Floating Point Custom Accumulator Intel® FPGA IP Parameters

Table 9.  Floating Point Custom Accumulator Intel® FPGA IP Parameters
Category Parameter Values Description
Input Data Floating point format single, double Choose the floating point format of the input data values. The output data values of the accumulator is in the same format.

The default is single.

maxMSBX — The maximum weight of the MSB of an input. For example, when adding probabilities in the 0 to 1 range set this weight to ceil(log2(1))=0. The xo output signal goes high when the MSB of an input value has a weight larger than maxMSBX. The result of the accumulation is then invalid. If you are unsure about the range of the inputs, then set the maxMSBX parameter to MSBA, at the possible expense of increased resource usage.

The default value is 12.

Accumulator Size MSBA — The weight of the MSB of the accumulator. For example, in a financial simulation, if the value of a stock cannot exceed 100,000 dollars, use a value of ceil(log2(100000))=17.

In a circuit simulation where the circuit adds numbers in the 0 to 1 range, for one year, at 400 MHz, use a value of ceil(log2(365 x 60 x 60 x 24 x 400 x 106))=54.

The ao output signal goes high when the MSB of the accumulated value has a weight larger than MSBA. The result of the accumulation is then invalid. Intel recommends adding a few guard bits to avoid possible accumulator overflow. A few guard bits have little impact on the accumulator size.

The default value is 20.

LSBA — The weight of the LSB of the accumulator and the accuracy of the accumulator. Because an N term accumulation can invalidate the log2(N) LSBs of the accumulator, you must consider the length of the accumulation and the range of the inputs when setting this parameter.

For example, if a 2-30 accuracy is required over an accumulation of 1024 numbers, then set the LSBA to:

(-30 - log2(1024)) = -40.

Any input 2e×1.F, where F is the mantissa and e is less than the LSBA will be shifted out of the accumulator. The au output signal goes high to indicate this situation.

The default value is -26.

Required Performance Target frequency Any positive integer value. Choose the frequency in MHz at which this core is expected to run. This together with the target device family determines the amount of pipelining in the core.

The default value is 200 MHz.

Optional Generate an enable port — Choose if the accumulator should have an enable signal.

This parameter is disabled by default.

Report — — Reports the latency of the device, which is the number of cycles it takes for an accumulation to propagate through the block from input to output.
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