Floating-Point Intel® FPGA IP User Guide

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ID 683750
Date 8/30/2024
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Document Table of Contents
Document Table of Contents x
1. About Floating-Point Intel® FPGA IP 2. Floating Point Custom Accumulator Intel® FPGA IP 3. Floating Point Functions IP 4. Floating-Point IP Cores User Guide Document Archives 5. Document Revision History for the Floating-Point Intel® FPGA IPUser Guide
1. About Floating-Point Intel® FPGA IP x
1.1. Installing and Licensing Intel® FPGA IP Cores 1.2. Design Flow 1.3. Upgrading IP Cores 1.4. Floating-Point IP Cores General Features 1.5. IEEE-754 Standard for Floating-Point Arithmetic 1.6. Non-IEEE-754 Standard Format 1.7. Floating-Points IP Cores Output Latency 1.8. VHDL Component Declaration 1.9. VHDL LIBRARY-USE Declaration
1.2. Design Flow x
1.2.1. IP Catalog and Parameter Editor 1.2.2. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition)
1.2.1. IP Catalog and Parameter Editor x
1.2.1.1. The Parameter Editor
1.2.2. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) x
1.2.2.1. IP Core Generation Output ( Quartus® Prime Pro Edition)
1.3. Upgrading IP Cores x
1.3.1. Migrating IP Cores to a Different Device
1.5. IEEE-754 Standard for Floating-Point Arithmetic x
1.5.1. Floating-Point Formats 1.5.2. Special Case Numbers 1.5.3. Rounding
1.5.1. Floating-Point Formats x
1.5.1.1. Single-Precision Format 1.5.1.2. Double-Precision Format 1.5.1.3. Single-Extended Precision Format
2. Floating Point Custom Accumulator Intel® FPGA IP x
2.1. Floating Point Custom Accumulator Intel® FPGA IP Features 2.2. Floating Point Custom Accumulator Intel® FPGA IP Output Latency 2.3. Floating Point Custom Accumulator Intel® FPGA IP Signals 2.4. Floating Point Custom Accumulator Intel® FPGA IP Parameters
3. Floating Point Functions IP x
3.1. Floating Point Functions IP Features 3.2. Floating Point Functions IP Output Latency 3.3. Floating Point Functions IP Target Frequency 3.4. Floating Point Functions IP Combined Target 3.5. Floating Point Functions IP Reset and Latency 3.6. Floating Point Functions IP Signals 3.7. Floating-Point Functions IP Parameters
1. About Floating-Point Intel® FPGA IP
2. Floating Point Custom Accumulator Intel® FPGA IP
3. Floating Point Functions IP
4. Floating-Point IP Cores User Guide Document Archives
5. Document Revision History for the Floating-Point Intel® FPGA IPUser Guide

1.5.3. Rounding

The IEEE-754 standard defines four types of rounding, which are:
  • Round to nearest with tie breaking to even
  • Round-toward-zero
  • Round-toward-positive-infinity
  • Round-toward-negative-infinity

Intel floating-point IPs support only the most commonly used rounding, which is round to nearest with tie breaking to even (TO_NEAREST). With round to nearest with tie breaking to even, the IP rounds the result to the nearest floating-point number. If the result is exactly halfway between two floating-point numbers, the IP rounds the result so that the LSB becomes a zero, which is even.

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