Floating-Point Intel® FPGA IP User Guide

ID 683750
Date 8/30/2024
Public
Document Table of Contents

1.7. Floating-Points IP Cores Output Latency

The IP cores measure the output latency in clock cycles and is different for each IP core. In some IP cores, the precision modes determine the number of clock cycles between the input and output result. When you select a mode, the options for latency are fixed for that mode.

For specific details about latency options, refer to the Output Latency section of your selected IP core in this user guide.