Visible to Intel only — GUID: eis1411634004390
Ixiasoft
Visible to Intel only — GUID: eis1411634004390
Ixiasoft
3.6. Floating Point Functions IP Signals
Port Name | Required | Description |
---|---|---|
clk | Yes | All input signals must be synchronous to this clock. |
areset | Yes | Active-high reset. Asynchronous for Arria 10 and Cyclone 10 GX devices; synchronous for Agilex devices. For asynchronous reset, deassert the reset signal synchronously to the input clock to avoid metastability issues. For synchronous reset, minimizing resets, whenever functionally safe, gives better performance. Synchronous reset may connect to all of the design, some of the design, or none of the design at all. Valid data is available at the the output L cycles after deasserting reset where L is the latency of the IP. |
en | No | Optional port. Allow calculation to take place when asserted. When deasserted, no operation will take place and the outputs are unchanged. |
a | Yes | Data input signal. |
b | Yes | Data input signal (where applicable). |
s | Yes | Select port for Add/Sub function. |
c | Yes | Data port for integer exponent port for LDExp function. |
Port Name | Required | Description |
---|---|---|
q | Yes | Data output signal. |