Visible to Intel only — GUID: eis1411544513593
Ixiasoft
Visible to Intel only — GUID: eis1411544513593
Ixiasoft
2.3. Floating Point Custom Accumulator Intel® FPGA IP Signals
Port Name | Required | Description |
---|---|---|
clk | Yes | All input signals, unless otherwise explicitly stated, must be synchronous to this clock |
areset | Yes | Active-high reset. Asynchronous for Arria 10 and Cyclone 10 GX devices; synchronous for Agilex devices. For asynchronous reset, deassert the reset signal synchronously to the input clock to avoid metastability issues. For synchronous reset, minimizing resets, whenever functionally safe, gives better performance. Synchronous reset may connect to all of the design, some of the design, or none of the design at all. Valid data is available at the the output L cycles after deasserting reset where L is the latency of the IP. |
en | No | Global enable signal. This port is optional. |
x | Yes | Data input port. |
n | Yes | Boolean port which signals the beginning of a new data set to be accumulated. This should go high together with the first element in the new data set and should go low the next cycle. The data sets may be of variable length and a new data set may be started at any time. The accumulation result for an input is available after the reported latency. |
Port Name | Required | Description |
---|---|---|
r | Yes | The running value of the accumulation. |
xo | Yes | The overflow flag for port x. The signal goes high when the exponent of the input x is larger than maxMSBX (refer to Floating Point Custom Accumulator Intel FPGA IP Parameters). The signal remains high for the entire data set. This flag invalidates port r. You should consider increasing maxMSBX. This flag also indicates infinity and NaN. |
xu | Yes | The underflow flag for port x. The signal goes high when the exponent of the input x is smaller than LSBA (refer to Floating Point Custom Accumulator Intel FPGA IP Parameters). The signal remains high for the entire data set. This flag does not invalidate port r. You should consider lowering LSBA. |
ao | Yes | The overflow flag for Accumulator. The signal goes high when the exponent of the accumulated value is larger than MSBA (refer to Floating Point Custom Accumulator Intel FPGA IP Parameters). The signal remains high for the entire data set. This flag invalidates port r. You should consider increasing MSBA. |