F-Tile Interlaken Intel® FPGA IP User Guide

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ID 683622
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Interlaken Intel® FPGA IP 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. F-Tile Interlaken IP Registers 7. F-Tile Interlaken Intel® FPGA IP User Guide Archives 8. Document Revision History for F-Tile Interlaken Intel FPGA IP User Guide
1. About the F-Tile Interlaken Intel® FPGA IP x
1.1. F-Tile Interlaken IP Features 1.2. F-Tile Interlaken IP Device Family Support 1.3. Device Speed Grade Support 1.4. F-Tile Interlaken IP Performance and Resources 1.5. F-Tile Interlaken IP Round-trip Latency 1.6. F-Tile Interlaken IP Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Generated File Structure 2.3. Specifying the F-Tile Interlaken IP Parameters and Options 2.4. Reference and System PLL Clock for your IP Design 2.5. Simulating the F-Tile Interlaken IP 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.4. Reference and System PLL Clock for your IP Design x
2.4.1. System PLL Configuration
3. Parameter Settings x
3.1. Analog Parameters
4. Functional Description x
4.1. Datapath Flow 4.2. Interlaken Look-aside Datapath Flow 4.3. Modes of Operation 4.4. Performance 4.5. IP Reset 4.6. M20K ECC Support 4.7. Out-of-Band Flow Control 4.8. 32-bit Soft CWBIN Counters
4.1. Datapath Flow x
4.1.1. Interlaken TX Path 4.1.2. Interlaken RX Path
4.1.1. Interlaken TX Path x
4.1.1.1. Transmit Path Blocks 4.1.1.2. In-Band Calendar Bits on Transmit Side
4.1.2. Interlaken RX Path x
4.1.2.1. Receive Path Blocks 4.1.2.2. In-Band Calendar Bits on Receive Side 4.1.2.3. RX Errored Packet Handling
4.1.2.3. RX Errored Packet Handling x
4.1.2.3.1. Example With Errors and In-Band Calendar Bits
4.2. Interlaken Look-aside Datapath Flow x
4.2.1. Interlaken Look-aside TX Path 4.2.2. Interlaken Look-aside RX Path
4.2.1. Interlaken Look-aside TX Path x
4.2.1.1. Transmit Path Blocks
4.2.2. Interlaken Look-aside RX Path x
4.2.2.1. Look-aside Receive Path Blocks 4.2.2.2. RX Error Handling
4.3. Modes of Operation x
4.3.1. Interleaved and Packet Modes 4.3.2. Multisegments 4.3.3. Interlaken Look-aside Mode
4.3.1. Interleaved and Packet Modes x
4.3.1.1. Transmit User Data Interface Examples 4.3.1.2. Receive User Data Interface Example
4.3.2. Multisegments x
4.3.2.1. Multi-Segment Interface Example
4.3.3. Interlaken Look-aside Mode x
4.3.3.1. Transmit User Data Interface Example 4.3.3.2. Receive User Data Interface Example
5. Interface Signals x
5.1. F-Tile Interlaken IP Clock and Reset Interface Signals 5.2. F-Tile Interlaken IP Transmit User Interface Signals 5.3. F-Tile Interlaken IP Receive User Interface Signals 5.4. F-Tile Interlaken IP Management Interface Signals 5.5. F-Tile Interlaken IP Reconfiguration Interface Signals 5.6. F-Tile Interlaken Link and Miscellaneous Signals
1. About the F-Tile Interlaken Intel® FPGA IP
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. F-Tile Interlaken IP Registers
7. F-Tile Interlaken Intel® FPGA IP User Guide Archives
8. Document Revision History for F-Tile Interlaken Intel FPGA IP User Guide

2.3. Specifying the F-Tile Interlaken IP Parameters and Options

The IP parameter editor allows you to quickly configure your custom IP variation. Perform the following steps to specify IP options and parameters in the Quartus® Prime Pro Edition software.

You must use the IP Catalog accessible from the Quartus® Prime Pro Edition Tools menu.

F-Tile Interlaken IP Parameter Editor
  1. In the Quartus® Prime Pro Edition software, click File > New Project Wizard to create a new Quartus® Prime project, or File > Open Project to open an existing Quartus® Prime project. The wizard prompts you to specify a device.
  2. Select the device family Intel Agilex 7 with F-Tile as your target device.
  3. In the IP Catalog (Tools > IP Catalog), locate and double-click F-Tile Interlaken Intel® FPGA IP Core. The New IP Variant window appears.
  4. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip> .ip.
  5. Click Create. The parameter editor appears.
  6. On the IP tab, specify the parameters and options for your IP variation, including one or more of the following. Refer to Parameter Settings for information about specific IP core parameters.
    • Specify parameters defining the IP functionality, port configurations, and device-specific features.
    • Specify options for processing the IP files in other EDA tools.
  7. Click Generate HDL. The Generation dialog box appears.
  8. Specify output file generation options, and then click Generate. The IP variation files generate according to your specifications.
    1. Select IP-XACT option to create an IP-XACT representation of your generated system.

      This selection generates the <ip_name>.ipxact file during the IP generation. The .ipxact file contains generic information about your IP. The IP variant-specific information such as reset and register values may vary across the IP variants.

  9. Optionally, click Generate Example Design tab in the parameter editor to generate a demonstration testbench and example design for your IP variation.
  10. Optionally, click the Analog Parameters tab to set the analog parameters of the F-Tile transceivers. These settings ensure the functionality of the design on hardware.
  11. Click Finish. The parameter editor adds the top-level .ip file to the project automatically. If you are prompted to manually add the .ip file to the project, click Project > Add/Remove Files in Project to add the file.
  12. After generating and instantiating your IP variation, make appropriate pin assignments to connect ports.
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