F-Tile Interlaken Intel® FPGA IP User Guide

ID 683622
Date 7/08/2024
Public
Document Table of Contents

2.5. Simulating the F-Tile Interlaken IP

You can simulate your Interlaken IP variation using any of the vendor-specific IEEE encrypted functional simulation models which are available in the new <instance name>/sim/<simulator> subdirectory of your project directory.

The F-Tile Interlaken Intel® FPGA IP supports the following simulators:
  • Synopsys* VCS* and VCS* MX
  • Siemens* EDA QuestaSim*
  • Cadence* Xcelium*
  • Questa*-Intel® FPGA Edition

The F-Tile Interlaken Intel® FPGA IP generates a Verilog HDL and VHDL simulation model and testbench. The IP parameter editor offers you the option of generating a Verilog HDL or VHDL simulation model for the IP, but the IP design example does not support a VHDL simulation model or testbench.

For more information about functional simulation models for Intel FPGA IPs, refer to the Simulating Intel FPGA Designs chapter in Intel Quartus Prime Pro Edition User Guide: Third-party Simulation.