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5.1. F-Tile Interlaken IP Clock and Reset Interface Signals
5.2. F-Tile Interlaken IP Transmit User Interface Signals
5.3. F-Tile Interlaken IP Receive User Interface Signals
5.4. F-Tile Interlaken IP Management Interface Signals
5.5. F-Tile Interlaken IP Reconfiguration Interface Signals
5.6. F-Tile Interlaken Link and Miscellaneous Signals
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4.3.1.2. Receive User Data Interface Example
The Interlaken IP Core can generate interleaved data transfers on the RX user data transfer interface. The IP core always toggles the irx_sob and irx_eob signals to indicate the beginning of the burst and end of the burst. In single segment mode, only irx_sob[1] toggles. Since only the single segment interleaved mode is supported, the irx_sob[1] and irx_num_valid[7:4] are the valid signals.
Figure 21. Interlaken IP Core Receiver Side Single Segment ExampleThe figure shows the timing diagram for an interleaved data transfer (8-word) in Interleaved mode.
This example illustrates the expected behavior of the Interlaken IP core application interface receive signals during data transfers from the IP core to the application on the RX user data transfer interface in interleaved single segment mode.
In cycle 1, the IP core asserts irx_sop[1] and irx_sob[1], indicating that this cycle is both the start of the burst and the start of the packet. The first word is MSB aligned at the top. The value the IP core drives on irx_chan indicates the data targets channel 2. You must sample irx_chan during cycles in which irx_sop[1] is asserted. The irx_chan output signal is not guaranteed to remain valid for the duration of the burst.
In cycle 2, the IP core asserts irx_eob, indicating the data the IP core transfers to the application in this clock cycle is the end of the burst. irx_num_valid[7:4] indicates all eight words are valid. However, the data in this cycle is not end of packet data. The IP core transfers at least one additional data burst in this packet, possibly interleaved with one or more bursts in packets that target different data channels.
Cycle 3 is a short burst with both irx_sop[1] and irx_eob asserted. The IP core drives the value of three on irx_num_valid[7:4] to indicate that three words of the eight-word irx_dout_words data bus are valid. The data is packed in the most significant words of irx_dout_words.The IP core drives the value of 4'b1011 on irx_eopbits to indicate that the data the IP core transfers to the application in this cycle are the final words of the packet, and that in the final word of the packet, only three bytes are valid data. The value the IP core drives on irx_chan indicates this burst targets channel 4.
In cycle 4, the irx_num_valid[7:4] signal has the value of zero, which means this cycle is an idle cycle.
In cycle 5, the IP core sends another single-cycle data burst to channel 2, by asserting irx_sob[1] and irx_eob to indicate this data is both the start and end of the burst. The IP core does not assert irx_sop[1], because this burst is not start of packet data. irx_eopbits has the value of 4'b0000, indicating this burst is also not end of packet data. This data follows the data burst transfered in cycles 1 and 2, within the same packet the IP core is sending to channel 2.
In cycle 6, the IP core sends a start of packet, single-cycle data burst to channel 3.
In cycles 7 and 8, the IP core sends a two-cycle data packet in one two-cycle burst. In cycle 8, the second data cycle, the IP core drives the value of two on irx_num_valid[7:4] and the value of 4'b1011 on irx_eopbits, to tell the application that in this clock cycle, the two most significant words of the data symbol contain valid data and the remaining words do not contain valid data, and that in the second of these two words, only the three most significant bytes contain valid data.