F-Tile Interlaken Intel® FPGA IP User Guide

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ID 683622
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Interlaken Intel® FPGA IP 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. F-Tile Interlaken IP Registers 7. F-Tile Interlaken Intel® FPGA IP User Guide Archives 8. Document Revision History for F-Tile Interlaken Intel FPGA IP User Guide
1. About the F-Tile Interlaken Intel® FPGA IP x
1.1. F-Tile Interlaken IP Features 1.2. F-Tile Interlaken IP Device Family Support 1.3. Device Speed Grade Support 1.4. F-Tile Interlaken IP Performance and Resources 1.5. F-Tile Interlaken IP Round-trip Latency 1.6. F-Tile Interlaken IP Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Generated File Structure 2.3. Specifying the F-Tile Interlaken IP Parameters and Options 2.4. Reference and System PLL Clock for your IP Design 2.5. Simulating the F-Tile Interlaken IP 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.4. Reference and System PLL Clock for your IP Design x
2.4.1. System PLL Configuration
3. Parameter Settings x
3.1. Analog Parameters
4. Functional Description x
4.1. Datapath Flow 4.2. Interlaken Look-aside Datapath Flow 4.3. Modes of Operation 4.4. Performance 4.5. IP Reset 4.6. M20K ECC Support 4.7. Out-of-Band Flow Control 4.8. 32-bit Soft CWBIN Counters
4.1. Datapath Flow x
4.1.1. Interlaken TX Path 4.1.2. Interlaken RX Path
4.1.1. Interlaken TX Path x
4.1.1.1. Transmit Path Blocks 4.1.1.2. In-Band Calendar Bits on Transmit Side
4.1.2. Interlaken RX Path x
4.1.2.1. Receive Path Blocks 4.1.2.2. In-Band Calendar Bits on Receive Side 4.1.2.3. RX Errored Packet Handling
4.1.2.3. RX Errored Packet Handling x
4.1.2.3.1. Example With Errors and In-Band Calendar Bits
4.2. Interlaken Look-aside Datapath Flow x
4.2.1. Interlaken Look-aside TX Path 4.2.2. Interlaken Look-aside RX Path
4.2.1. Interlaken Look-aside TX Path x
4.2.1.1. Transmit Path Blocks
4.2.2. Interlaken Look-aside RX Path x
4.2.2.1. Look-aside Receive Path Blocks 4.2.2.2. RX Error Handling
4.3. Modes of Operation x
4.3.1. Interleaved and Packet Modes 4.3.2. Multisegments 4.3.3. Interlaken Look-aside Mode
4.3.1. Interleaved and Packet Modes x
4.3.1.1. Transmit User Data Interface Examples 4.3.1.2. Receive User Data Interface Example
4.3.2. Multisegments x
4.3.2.1. Multi-Segment Interface Example
4.3.3. Interlaken Look-aside Mode x
4.3.3.1. Transmit User Data Interface Example 4.3.3.2. Receive User Data Interface Example
5. Interface Signals x
5.1. F-Tile Interlaken IP Clock and Reset Interface Signals 5.2. F-Tile Interlaken IP Transmit User Interface Signals 5.3. F-Tile Interlaken IP Receive User Interface Signals 5.4. F-Tile Interlaken IP Management Interface Signals 5.5. F-Tile Interlaken IP Reconfiguration Interface Signals 5.6. F-Tile Interlaken Link and Miscellaneous Signals
1. About the F-Tile Interlaken Intel® FPGA IP
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. F-Tile Interlaken IP Registers
7. F-Tile Interlaken Intel® FPGA IP User Guide Archives
8. Document Revision History for F-Tile Interlaken Intel FPGA IP User Guide

5.5. F-Tile Interlaken IP Reconfiguration Interface Signals

Table 31.  Transceiver Reconfiguration Interface Signals
Signal Name Width (Bits) I/O Direction Available In Description
reconfig_xcvr_clk 1 Input Interlaken and Interlaken Look-aside mode Transceiver reconfiguration interface clock. Supported frequency range 100-250MHz.
reconfig_xcvr_reset 1 Input Active-high synchronous reset. Assert this signal to reset the transceiver reconfiguration interface.
reconfig_xcvr_read 1 Input Read access to the hard PCS registers.
reconfig_xcvr_write 1 Input Write access to the hard PCS registers.
reconfig_xcvr_address 18+5 Input Address to access the hard PCS registers. This signal holds both the hard PCS register offset and the transceiver channel being addressed.
  • 18-bits for address
  • 5-bits for lane selection
reconfig_xcvr_writedata 32 Input When reconfig_write is high, reconfig_writedata holds valid write data.
reconfig_xcvr_readdata 32 Output After user logic asserts the reconfig_read signal, when the IP core deasserts the signal, reconfig_readdata holds valid read data.
reconfig_xcvr_readdatavalid 1 Output Valid signal for reconfig_xcvr_readdata.
reconfig_xcvr_waitrequest 1 Output Busy signal for reconfig_readdata.
reconfig_xcvr_byteenable 4 Input Transceiver reconfiguration byte enable signal.
Table 32.  Interlaken Reconfiguration Interface SignalsThese signals are only available for PAM4 mode.
Signal Name Width (Bits) I/O Direction Available In Description
reconfig_ilk_clk 1 Input Interlaken mode Interlaken reconfiguration interface clock. Supported frequency range 100-250MHz.
reconfig_ilk_reset 1 Input Active-high synchronous reset. Assert this signal to reset the Interlaken reconfiguration interface.
reconfig_ilk_read 1 Input Read access to the Interlaken reconfiguration registers.
reconfig_ilk_write 1 Input Write access to the Interlaken reconfiguration registers.
reconfig_ilk_address 14+3 Input Address to access the Interlaken reconfiguration registers.
  • 14-bits for address
  • 3-bits for FEC selection
reconfig_ilk_writedata 32 Input When reconfig_write is high, reconfig_writedata holds valid write data.
reconfig_ilk_readdata 32 Output After user logic asserts the reconfig_read signal, when the IP core deasserts the signal, reconfig_readdata holds valid read data.
reconfig_ilk_readdatavalid 1 Output Valid signal for reconfig_ilk_readdata.
reconfig_ilk_waitrequest 1 Output Busy signal for reconfig_readdata.
reconfig_ilk_byteenable 4 Input Interlaken reconfiguration byte enable signal.
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