Visible to Intel only — GUID: rup1614291606215
Ixiasoft
Visible to Intel only — GUID: rup1614291606215
Ixiasoft
4.1.2.3.1. Example With Errors and In-Band Calendar Bits
In cycle 1, the Interlaken IP core asserts irx_sop[1] when data is ready on irx_dout_words. When the Interlaken IP core asserts irx_sop[1], it also asserts the correct value on irx_chan to tell the application the data channel destination of the data. In this example, the value 2 on irx_chan tells the application that the data should be sent to channel number 2.
- irx_num_valid[7:4] at the value of 4'b0111 to indicate the current data symbol contains seven 64-bit words of valid data.
- irx_eopbits[3] high to indicate the current cycle is an EOP cycle.
- irx_eopbits[2:0] at the value of 3'b011 to indicate that only three bytes of the final valid data word are valid data bytes.
The application is responsible for discarding the errored packet when it detects that the IP core has asserted the irx_err signal. Following the corrupted packet, the IP core waits two idle cycles and then transfers a valid 139-byte packet.