F-Tile Interlaken Intel® FPGA IP User Guide

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ID 683622
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Interlaken Intel® FPGA IP 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. F-Tile Interlaken IP Registers 7. F-Tile Interlaken Intel® FPGA IP User Guide Archives 8. Document Revision History for F-Tile Interlaken Intel FPGA IP User Guide
1. About the F-Tile Interlaken Intel® FPGA IP x
1.1. F-Tile Interlaken IP Features 1.2. F-Tile Interlaken IP Device Family Support 1.3. Device Speed Grade Support 1.4. F-Tile Interlaken IP Performance and Resources 1.5. F-Tile Interlaken IP Round-trip Latency 1.6. F-Tile Interlaken IP Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Generated File Structure 2.3. Specifying the F-Tile Interlaken IP Parameters and Options 2.4. Reference and System PLL Clock for your IP Design 2.5. Simulating the F-Tile Interlaken IP 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.4. Reference and System PLL Clock for your IP Design x
2.4.1. System PLL Configuration
3. Parameter Settings x
3.1. Analog Parameters
4. Functional Description x
4.1. Datapath Flow 4.2. Interlaken Look-aside Datapath Flow 4.3. Modes of Operation 4.4. Performance 4.5. IP Reset 4.6. M20K ECC Support 4.7. Out-of-Band Flow Control 4.8. 32-bit Soft CWBIN Counters
4.1. Datapath Flow x
4.1.1. Interlaken TX Path 4.1.2. Interlaken RX Path
4.1.1. Interlaken TX Path x
4.1.1.1. Transmit Path Blocks 4.1.1.2. In-Band Calendar Bits on Transmit Side
4.1.2. Interlaken RX Path x
4.1.2.1. Receive Path Blocks 4.1.2.2. In-Band Calendar Bits on Receive Side 4.1.2.3. RX Errored Packet Handling
4.1.2.3. RX Errored Packet Handling x
4.1.2.3.1. Example With Errors and In-Band Calendar Bits
4.2. Interlaken Look-aside Datapath Flow x
4.2.1. Interlaken Look-aside TX Path 4.2.2. Interlaken Look-aside RX Path
4.2.1. Interlaken Look-aside TX Path x
4.2.1.1. Transmit Path Blocks
4.2.2. Interlaken Look-aside RX Path x
4.2.2.1. Look-aside Receive Path Blocks 4.2.2.2. RX Error Handling
4.3. Modes of Operation x
4.3.1. Interleaved and Packet Modes 4.3.2. Multisegments 4.3.3. Interlaken Look-aside Mode
4.3.1. Interleaved and Packet Modes x
4.3.1.1. Transmit User Data Interface Examples 4.3.1.2. Receive User Data Interface Example
4.3.2. Multisegments x
4.3.2.1. Multi-Segment Interface Example
4.3.3. Interlaken Look-aside Mode x
4.3.3.1. Transmit User Data Interface Example 4.3.3.2. Receive User Data Interface Example
5. Interface Signals x
5.1. F-Tile Interlaken IP Clock and Reset Interface Signals 5.2. F-Tile Interlaken IP Transmit User Interface Signals 5.3. F-Tile Interlaken IP Receive User Interface Signals 5.4. F-Tile Interlaken IP Management Interface Signals 5.5. F-Tile Interlaken IP Reconfiguration Interface Signals 5.6. F-Tile Interlaken Link and Miscellaneous Signals
1. About the F-Tile Interlaken Intel® FPGA IP
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. F-Tile Interlaken IP Registers
7. F-Tile Interlaken Intel® FPGA IP User Guide Archives
8. Document Revision History for F-Tile Interlaken Intel FPGA IP User Guide

3.1. Analog Parameters

Analog parameter settings allow you to tune the transceiver analog functions in the FGT and FHT PMAs while designing high-speed serial protocol solutions. Use this feature to compensate for signal losses for high data rate communication.
Note: The design level HSSI_PARAMETER settings in the .qsf file take precedence over the Analog Parameters GUI settings.
Figure 6. Analog Parameter Options for FGT PMA in Parameter Editor
Table 16.  FGT TX Equalization (EQ) Analog Parameter Options
Parameter Values Description
FGT TXEQ Post Tap 1, 1.0 step size 0 to 19 Options for FGT TX EQ Post Tap 1, in 1.0 step size increments. Default value is 0.
FGT TXEQ Pre Tap 1, 1.0 step size 0 to 15 Options for FGT TX EQ Pre Tap 1, in 1.0 step size increments. Default value is 5.
FGT TXEQ Pre Tap 2, 1.0 step size 0 to 7

Options for FGT TX EQ Pre Tap 2, in 1.0 step size increments. Default value is 0.

FGT TXEQ Main Tap, 1.0 step size 0 to 55 Options for FGT TX EQ Main Tap, in 1.0 step size increments. Default value is 35.
Table 17.  FGT RX Analog Parameter Options
Parameter Values Description
Select FGT RX Onchip Termination RX_ONCHIP_TERMINATION_R_1(85 Ohms)

RX_ONCHIP_TERMINATION_R_2(100 ohms)

Selects FGT RX termination resistor setting. Default value is RX_ONCHIP_TERMINATION_R_1(85 Ohms).
Enable FGT RX AC Couple DISABLE

ENABLE

Enable RX external AC coupling setting. Default value is ENABLE.
Enable FGT VSR mode VSR_MODE_LOW_LOSS

VSR_MODE_HIGH_LOSS

VSR_MODE_DISABLE

Enable VSR mode setting. Default value is VSR_MODE_DISABLE.
RXEQ VGA Gain 0 to 63 Options for RX EQ VGA gain value, in 1.0 step size increments. Default value is 0.
Note: This parameter is only available when the Adaptation mode is set to manual in RX Datapath Options.
RXEQ High Frequency Boost 0 to 63 Options for RX EQ high frequency boost value, in 1.0 step size increments. Default value is 0.
Note: This parameter is only available when the Adaptation mode is set to manual in RX Datapath Options.
RXEQ DFE Data Tap1 0 to 63 Options for RX EQ DFE data tap1 value, in 1.0 step size increments. Default value is 0.
Note: This parameter is only available when the Adaptation mode is set to manual in RX Datapath Options.
Figure 7. Analog Parameter Options for FHT PMA in Parameter Editor
Table 18.  FHT TX Analog Parameter Options
Parameter Values Description
Enable FHT TX P&N Invert Disabled

Enabled

Enable FHT TX P and N inversion. Default value is Disabled.
Enable FHT TXOUT Tristate Disabled

Enabled

Enable tristate on FHT TX serial outputs. Default value is Disabled.
Select FHT TX Termination TXTERM_OFFSET_P0(90 Ohms)

TXTERM_OFFSET_M1(96.8 Ohms)

Selects FHT TX termination resistor setting. Default value is TXTERM_OFFSET_P0(90 Ohms).
Table 19.  FHT TX Equalization (EQ) Analog Parameter Options
Parameter Values Description

Post-Cursor 4, 0.25 step size

-8.0 to +7.75 FHT post tap 4 coefficients, 0.25 step size. Default value is 0.0.
Post-Cursor 3, 0.25 step size -8.0 to +7.75 FHT post tap 3 coefficients, 0.25 step size. Default value is 0.0.
Post-Cursor 2, 0.25 step size -8.0 to +7.75 FHT post tap 2 coefficients, 0.25 step size. Default value is 0.0.
Post-Cursor 1, 0.5 step size -16.0 to +15.5 FHT post tap 1 coefficient, 0.5 step size. Default value is 0.0.
Main-Cursor,0.5 step size 0.0 to 41.5 FHT main tap coefficient, 0.5 step size. Default value is 41.5.
Pre-Cursor 1,0.5 step size -16.0 to +15.5 FHT pre tap 1 coefficient, 0.5 step size. Default value is 0.0.
Pre-Cursor 2,0.25 step size -8.0 to +7.75 FHT pre tap 2 coefficients, 0.25 step size. Default value is 0.0.
Pre-Cursor 3,0.25 step size -8.0 to +7.75 FHT pre tap 3 coefficients, 0.25 step size. Default value is 0.0.
Table 20.  FHT RX Analog Parameter Options
Parameter Values Description
Enable FHT RX P&N Invert Disabled

Enabled

Enable FHT RX P and N inversion. Default value is Disabled.
Select FHT RX Termination RXTERM_OFFSET_P0(90 Ohms)

RXTERM_OFFSET_P2(94.6 Ohms)

RXTERM_OFFSET_P3(97.7 Ohms)

RXTERM_OFFSET_P4(100 Ohms)

RXTERM_OFFSET_P5(102.3 Ohms)

RXTERM_OFFSET_P6(105.4 Ohms)

RXTERM_OFFSET_P7(107.7 Ohms)

RXTERM_OFFSET_P8(110 Ohms)

RXTERM_OFFSET_M4(80.8 Ohms)

RXTERM_OFFSET_M5(83.1 Ohms)

RXTERM_OFFSET_M6(85.4 Ohms)

RXTERM_OFFSET_M7(87.7 Ohms)

Selects FHT RX termination resistor setting. Default value is RXTERM_OFFSET_P0(90 Ohms).
Select FHT external AC Cap EXTERNAL_AC_CAP_ENABLE

EXTERNAL_AC_CAP_DISABLE

Enable external AC coupling capacitance. Default value is EXTERNAL_AC_CAP_ENABLE.
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