Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 9/30/2024
Public
Document Table of Contents

6.1.2. Avalon® Memory Mapped Clock Crossing Bridge Intel® FPGA IP

The Avalon® Memory Mapped Clock Crossing Bridge Intel® FPGA IP transfers Avalon® memory mapped commands and responses between different clock domains. You can also use the Avalon® Memory Mapped Clock Crossing Bridge between AXI hosts and agents of different clock domains.

The Avalon® Memory Mapped Clock Crossing Bridge uses asynchronous FIFOs to implement clock crossing logic. The bridge parameters control the depth of the command and response FIFOs in both the host and agent clock domains. If the number of active reads exceeds the depth of the response FIFO, the Clock Crossing Bridge stops sending reads.

To maintain throughput for high-performance applications, increase the response FIFO depth from the default minimum depth, which is twice the maximum burst size.

Note: When you use the FIFO-based clock crossing a Platform Designer system, the DC FIFO is automatically inserted in the Platform Designer system. The reset inputs for the DC FIFO connect to the reset sources for the connected host and agent components on either side of the DC FIFO. For this configuration, you must assert both the resets on the host and the agent sides at the same time to ensure the DC FIFO resets properly. Alternatively, you can drive both resets from the same reset source to guarantee that the DC FIFO resets properly.
Note: The clock crossing bridge includes appropriate SDC constraints for its internal asynchronous FIFOs. For these SDC constraints to work correctly, do not set false paths on the pointer crossings in the FIFOs. Do not split the bridge’s clocks into separate clock groups when you declare SDC constraints; the split has the same effect as setting false paths.