Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit User Guide

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ID 683591
Date 9/27/2019
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Kit
2. Getting Started x
2.1. About the Intel® Quartus® Prime Software 2.2. Development Kit Package 2.3. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Setting up the Development Kit 3.2. Factory Default Switch and Jumper Settings
4. Development Kit Components x
4.1. Development Kit Overview 4.2. Intel® Stratix® 10 TX FPGA 4.3. MAX® V CPLD 4.4. FPGA Configuration 4.5. Status and Setup Elements 4.6. User Input-Output Components 4.7. Clocks 4.8. Transceiver Channels 4.9. Communication Ports 4.10. Flash Memory 4.11. System Power
4.4. FPGA Configuration x
4.4.1. Configuring the FPGA over Embedded Intel® FPGA Download Cable II 4.4.2. Configuring the FPGA through Flash Memory 4.4.3. Configuring the FPGA over External Intel® FPGA Download Cable
4.7. Clocks x
4.7.1. Transceiver Dedicated Clocks 4.7.2. General-Purpose Clocks 4.7.3. Embedded Intel® FPGA Download Cable II Clock
4.10. Flash Memory x
4.10.1. Parallel NOR Flash Memory 4.10.2. EPCQL Flash Memory
4.11. System Power x
4.11.1. Power Guidelines 4.11.2. Power Supply 4.11.3. Power Management 4.11.4. Power Distribution System 4.11.5. Thermal Limitations and Protection Guidelines
5. Board Test System x
5.1. Preparing the Development Kit 5.2. Running the Board Test System 5.3. Using the Board Test System 5.4. Simple Socket Server
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The System Info Tab 5.3.3. The GPIO Tab 5.3.4. The EPCQ Tab 5.3.5. The FMC+ Tab 5.3.6. The PAM4 Tab 5.3.7. The MXP Tab 5.3.8. The QSFPDD1x2 Tab 5.3.9. The QSFPDD2x1 Tab 5.3.10. Power Monitor 5.3.11. Clock Controller
A. Additional Information x
A.1. Add SmartVID settings in QSF file A.2. Safety and Regulatory Information A.3. Compliance and Conformity Information
A.2. Safety and Regulatory Information x
A.2.1. Safety Warnings A.2.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

4.6. User Input-Output Components

This section describes the user I/O interface to the FPGA. The following I/O elements are described:
  • User-defined Pushbuttons
  • User-defined DIP Switches
  • User-defined LEDs

User-Defined Pushbuttons

This development kit includes 4 user-defined pushbuttons and 4 system pushbuttons that allow you to interact with the Intel® Stratix® 10 TX FPGA. When you press and hold down the pushbutton, the device pin is set to logic 0; when you release the pushbutton, the device pin is set to logic 1. There is no board-specific function for these general user pushbuttons.

The table below lists the pushbuttons, schematic signal names and their corresponding Intel® Stratix® 10 TX FPGA device pin numbers.

Table 8.  User-Defined Pushbuttons
Board Reference Schematic Signal Name Description Intel® Stratix® 10 TX Pin Number
S1 USER_PB0 User Pushbutton N19
S2 USER_PB1 User Pushbutton P19
S3 USER_PB2 User Pushbutton L23
S4 USER_PB3 User Pushbutton M23
S5 PGM_SEL System Pushbutton N/A
S6 PGM_CONFIG System Pushbutton N/A
S7 MAX_RESETn System Pushbutton N/A
S8 CPU_RESETn System Pushbutton R35

User-Defined DIP Switch

Board reference SW4 and SW5 are two 4-pin DIP switches. The switches are user-defined and provides additional FPGA input control. When the switch is in the OPEN or OFF position, a logic 1 is selected. When the switch is in the CLOSED or ON position, a logic 0 is selected. There is no board-specific function for these switches.

The table below lists the schematic signal names of each DIP switch and their corresponding Intel® Stratix® 10 TX FPGA pin numbers.

Table 9.  User-Defined DIP Switch
Board Reference Schematic Signal Name Intel® Stratix® 10 TX Pin Number
SW4.4 USER_DIP0 G23
SW4.3 USER_DIP1 G24
SW4.2 USER_DIP2 K23
SW4.1 S10_UNLOCK K22

User-Defined LEDs

The development board includes 8 user-defined LEDs. Board references D12 through D19 are user LEDs that allow status and debugging signals to be driven to the LEDs from the designs loaded into the Intel® Stratix® 10 TX FPGA device. The LEDs illuminate when a logic 0 is driven and turns off when a logic 1 is driven. There is no board-specific function for these LEDs.

The table below lists the user-defined schematic signal names and their corresponding Intel® Stratix® 10 TX FPGA device pin numbers.

Table 10.  User-Defined LEDs
Board Reference Schematic Signal Name Intel® Stratix® 10 TX Pin Number
D12 USER_LED0 G31
D13 USER_LED1 H31
D14 USER_LED2 G32
D15 USER_LED3 G33
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