Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit User Guide

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ID 683591
Date 9/27/2019
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Kit
2. Getting Started x
2.1. About the Intel® Quartus® Prime Software 2.2. Development Kit Package 2.3. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Setting up the Development Kit 3.2. Factory Default Switch and Jumper Settings
4. Development Kit Components x
4.1. Development Kit Overview 4.2. Intel® Stratix® 10 TX FPGA 4.3. MAX® V CPLD 4.4. FPGA Configuration 4.5. Status and Setup Elements 4.6. User Input-Output Components 4.7. Clocks 4.8. Transceiver Channels 4.9. Communication Ports 4.10. Flash Memory 4.11. System Power
4.4. FPGA Configuration x
4.4.1. Configuring the FPGA over Embedded Intel® FPGA Download Cable II 4.4.2. Configuring the FPGA through Flash Memory 4.4.3. Configuring the FPGA over External Intel® FPGA Download Cable
4.7. Clocks x
4.7.1. Transceiver Dedicated Clocks 4.7.2. General-Purpose Clocks 4.7.3. Embedded Intel® FPGA Download Cable II Clock
4.10. Flash Memory x
4.10.1. Parallel NOR Flash Memory 4.10.2. EPCQL Flash Memory
4.11. System Power x
4.11.1. Power Guidelines 4.11.2. Power Supply 4.11.3. Power Management 4.11.4. Power Distribution System 4.11.5. Thermal Limitations and Protection Guidelines
5. Board Test System x
5.1. Preparing the Development Kit 5.2. Running the Board Test System 5.3. Using the Board Test System 5.4. Simple Socket Server
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The System Info Tab Board Information System-MAX Control JTAG Chain 5.3.3. The GPIO Tab 5.3.4. The EPCQ Tab 5.3.5. The FMC+ Tab 5.3.6. The PAM4 Tab 5.3.7. The MXP Tab 5.3.8. The QSFPDD1x2 Tab 5.3.9. The QSFPDD2x1 Tab 5.3.10. Power Monitor 5.3.11. Clock Controller
A. Additional Information x
A.1. Add SmartVID settings in QSF file A.2. Safety and Regulatory Information A.3. Compliance and Conformity Information
A.2. Safety and Regulatory Information x
A.2.1. Safety Warnings A.2.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

5.3.2. The System Info Tab

The System Info tab shows information about the board's current configuration. The tab displays system-MAX V control setting, the board's MAC address, and other details stored on the board.

Figure 15. The System Info Tab

The following sections describe the controls on the System Info tab.

Board Information

The Board Information control displays static information about your board. The information is displayed after configuring the FPGA with GPIO/FLASH design.
  • Board Name: Indicates the official name of the board given by the BTS.
  • Board P/N: Indicates the part number of the board.
  • Serial Number: Indicates the serial number of the board.
  • Board Revision: Indicates the revision of the board.
  • MAC Address : Indicates the MAC Address of the board.

System-MAX Control

The MAX V register control allows you to view and change the current MAX V register values as described in the table below. Change to the register values with the GUI take effect immediately.

Table 21.  MAX V Registers
MAX V Register Values Description
Configure

Resets the system and reloads the FPGA with a design from flash memory based on the other MAX V register values.

PSO Sets the MAX V PSO register
PSR

Sets the MAX V PSR register. Allows PSR to determine the page of flash memory to use for FPGA reconfiguration. The numerical values in the list corrresponds to the page of flash memory to load during the FPGA reconfiguration.

PSS

Displays the MAX V PSS register value. Allows the PSS to determine the page of flash memory to use for FPGA reconfiguration.

MAX Ver

Indicates the version of MAX V code currently running on the board.The MAX V code resides in the <package dir>\examples\max5 directory. Newer revisions of this code may be available on the Stratix 10 Transceiver Signal Integrity Development Kit link on the Intel website.

JTAG Chain

The JTAG chain control shows all the devices currently in the JTAG chain.
Note: When switch SW 1-2 (MAX BYPASS) is set to 1 (OFF), the JTAG chain includes the MAX V device. When set to 0 (ON), the MAX V device is removed from the JTAG chain. System MAX and FPGA must be in the JTAG chain when running the BTS GUI.
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