Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit User Guide

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ID 683591
Date 9/27/2019
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Kit
2. Getting Started x
2.1. About the Intel® Quartus® Prime Software 2.2. Development Kit Package 2.3. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Setting up the Development Kit 3.2. Factory Default Switch and Jumper Settings
4. Development Kit Components x
4.1. Development Kit Overview 4.2. Intel® Stratix® 10 TX FPGA 4.3. MAX® V CPLD 4.4. FPGA Configuration 4.5. Status and Setup Elements 4.6. User Input-Output Components 4.7. Clocks 4.8. Transceiver Channels 4.9. Communication Ports 4.10. Flash Memory 4.11. System Power
4.4. FPGA Configuration x
4.4.1. Configuring the FPGA over Embedded Intel® FPGA Download Cable II 4.4.2. Configuring the FPGA through Flash Memory 4.4.3. Configuring the FPGA over External Intel® FPGA Download Cable
4.7. Clocks x
4.7.1. Transceiver Dedicated Clocks 4.7.2. General-Purpose Clocks 4.7.3. Embedded Intel® FPGA Download Cable II Clock
4.10. Flash Memory x
4.10.1. Parallel NOR Flash Memory 4.10.2. EPCQL Flash Memory
4.11. System Power x
4.11.1. Power Guidelines 4.11.2. Power Supply 4.11.3. Power Management 4.11.4. Power Distribution System 4.11.5. Thermal Limitations and Protection Guidelines
5. Board Test System x
5.1. Preparing the Development Kit 5.2. Running the Board Test System 5.3. Using the Board Test System 5.4. Simple Socket Server
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The System Info Tab 5.3.3. The GPIO Tab 5.3.4. The EPCQ Tab 5.3.5. The FMC+ Tab 5.3.6. The PAM4 Tab 5.3.7. The MXP Tab 5.3.8. The QSFPDD1x2 Tab 5.3.9. The QSFPDD2x1 Tab 5.3.10. Power Monitor 5.3.11. Clock Controller
A. Additional Information x
A.1. Add SmartVID settings in QSF file A.2. Safety and Regulatory Information A.3. Compliance and Conformity Information
A.2. Safety and Regulatory Information x
A.2.1. Safety Warnings A.2.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

3.1. Setting up the Development Kit

To prepare and apply power to the board, perform the following steps:
  1. The Intel® Stratix® 10 TX transceiver signal integrity development kit ships with its board switches preconfigured to support the design examples in the kit. If you suspect your board might not be correctly configured with the default settings, follow the instructions in the Factory Default Switch and Jumper Settings to return the board to its factory settings before proceeding forward.
  2. The development kit ships with design examples stored in the flash device. The POWER-ON slide switch (SW10) is provided to turn the board ON or OFF.
    Note: When the power cord is plugged into connector J46 of the Intel® Stratix® 10 transceiver signal integrity development kit, 12V_IN and 3.3V_STBY are present on to the board with switch SW10 in the OFF position. These voltages are restricted to a small area of the board. When switch SW10 is placed to ON position, all voltages planes have power at this point.
  3. Set the POWER-ON switch SW10 to the ON position. When power is supplied to the board, three green LEDs (D23, D24 and D25) illuminate and an amber LED (D5) extinguishes indicating that the board has power. If the amber LED (D5) illuminates, it indicates that one or more power supply is incorrect.
  4. RESET button (S7) is connected to the MAX® V CPLD (MAX_RESETn pin) that is used for AvST configuration. When this button is pressed, the MAX® V CPLD initiates a reloading of the stored image from the flash memory using AvST configuration mode. The image loaded right after power cycle or MAX® V reset depends on FACTORY_LOAD SW5.1 settings.
    • OFF(1) - factory load
    • ON (0) - user defined load #1
Page selection can be changed by the PGMSEL button (S5) when the board is powered on, and PGM_CONFIG (S6) is used to reconfigure FPGA with corresponding page which is indicated by PGM_LED0, PGM_LED1 or PGM_LED2.
CAUTION:
Use only the supplied power supply. Power regulation circuits on the board can get damaged by power supplies with greater voltage.

The MAX® V CPLD device on the board contains a parallel flash loader II (PFL II) megafunction. If AvST configuration mode is selected, after a POWER-ON or RESET (reconfiguration) event, the MAX® V CPLD configures the Intel® Stratix® 10 FPGA in AvST mode with either factory design or user design depending on the setting of FACTORY_LOAD.

This development kit includes a MAX® V CPLD design which contains the PFL II megafunction. The design resides in the <package dir>\examples\max5 directory. When configuration is complete, LED D21 (CONF_DONE) illumintes signaling that the Intel® Stratix® 10 TX FPGA device is configured successfully. If the configuration fails, the LED D19 (ERROR) illuminates.

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