Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit User Guide

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ID 683591
Date 9/27/2019
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Kit
2. Getting Started x
2.1. About the Intel® Quartus® Prime Software 2.2. Development Kit Package 2.3. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Setting up the Development Kit 3.2. Factory Default Switch and Jumper Settings
4. Development Kit Components x
4.1. Development Kit Overview 4.2. Intel® Stratix® 10 TX FPGA 4.3. MAX® V CPLD 4.4. FPGA Configuration 4.5. Status and Setup Elements 4.6. User Input-Output Components 4.7. Clocks 4.8. Transceiver Channels 4.9. Communication Ports 4.10. Flash Memory 4.11. System Power
4.4. FPGA Configuration x
4.4.1. Configuring the FPGA over Embedded Intel® FPGA Download Cable II 4.4.2. Configuring the FPGA through Flash Memory 4.4.3. Configuring the FPGA over External Intel® FPGA Download Cable
4.7. Clocks x
4.7.1. Transceiver Dedicated Clocks 4.7.2. General-Purpose Clocks 4.7.3. Embedded Intel® FPGA Download Cable II Clock
4.10. Flash Memory x
4.10.1. Parallel NOR Flash Memory 4.10.2. EPCQL Flash Memory
4.11. System Power x
4.11.1. Power Guidelines 4.11.2. Power Supply 4.11.3. Power Management 4.11.4. Power Distribution System 4.11.5. Thermal Limitations and Protection Guidelines
5. Board Test System x
5.1. Preparing the Development Kit 5.2. Running the Board Test System 5.3. Using the Board Test System 5.4. Simple Socket Server
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The System Info Tab 5.3.3. The GPIO Tab 5.3.4. The EPCQ Tab 5.3.5. The FMC+ Tab 5.3.6. The PAM4 Tab 5.3.7. The MXP Tab 5.3.8. The QSFPDD1x2 Tab 5.3.9. The QSFPDD2x1 Tab Status Port PMA Setting Data Type Error Control Run Control 5.3.10. Power Monitor 5.3.11. Clock Controller
A. Additional Information x
A.1. Add SmartVID settings in QSF file A.2. Safety and Regulatory Information A.3. Compliance and Conformity Information
A.2. Safety and Regulatory Information x
A.2.1. Safety Warnings A.2.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

5.3.9. The QSFPDD2x1 Tab

The QSFPDD2x1 Tab allows you to run transceivers QSFPDD2x1 loopback tests on your board. Install two QSFPDD loopback modules into QSFPDD2x1 interface, configure the FPGA with QSFPDD2x1 image.

Figure 28. The QSFPDD2x1 Tab

The following sections describe the controls on the QSFPDD2x1 tab.

Status

The Status control displays the following status information during the loopback test:
  • PLL lock: Shows the PLL locked or unlocked state
  • Pattern Sync: Shows the pattern synced or not state. The pattern is considered synced when the start of the data sequence is detected.
  • Details: Shows the details of PLL lock, pattern status and error bits of each channel.
Figure 29. QSFPDD2X1 Status

Port

Use the following controls to select an interface to apply PMA settings, data type and error control:
  • QSFPDD2x1

PMA Setting

Allows you to make changes to the PMA parameters that affect the active transceiver interface. The following settings are available for analysis:
  • Serial Loopback: Routes signals between the transmitter and the receiver.
  • VOD: Specifies the voltage output differential of the transmitter buffer.
  • Pre-emphasis tap:
    • Pre-tap 1: Specifies the amount of pre-emphasis on the first pre-tap of the transmitter buffer.
    • Pre-tap 2: Specifies the amount of pre-emphasis on the second pre-tap of the transmitter buffer.
    • Pre-tap 3: Specifies the amount of pre-emphasis on the third pre-tap of the transmitter buffer.
    • Post-tap 1: Specifies the amount of pre-emphasis on the post-tap of the transmitter buffer.
  • Equalizer: Specifies the RX tuning mode for receiver equalizer.
Figure 30. QSFPDD2X1 PMA Setting

Data Type

The Data Type control specifies the type of data pattern contained in the transactions. Select the following available data types for analysis:
  • PRBS7: pseudo-random 7-bit sequences (default)
  • PRBS15: pseudo-random 15-bit sequences
  • PRBS23: pseudo-random 23-bit sequences
  • PRBS31: pseudo-random 31-bit sequences
  • HF: Selects highest frequency divide-by-2 data pattern 10101010.
  • LF: Selects lowest frequency divide-by-33 data pattern.

Error Control

This control displays data errors detected during analysis and allows you to insert errors:
  • Detected Errors: Displays the number of data errors detected in the received bit stream.
  • Inserted Errrors: Displays the number of errors inserted into the transmit data stream.
  • Bit Error Rate: Displays the error rate of data transaction.
  • Insert Error: Insert a one-word error into the transmit data stream each time you click the button. Insert Error is only enabled during transaction performance analysis.
  • Clear: Resets the Detected Errors counter and Inserted Errors counter to zeros.

Run Control

TX and RX performance bars: Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve.

Start: This toggle button initiates and stops the tests.

Tx (Mbps) and Rx (Mbps): Show the number of bytes of data analyzed per second.

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