Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit User Guide

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ID 683591
Date 9/27/2019
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Kit
2. Getting Started x
2.1. About the Intel® Quartus® Prime Software 2.2. Development Kit Package 2.3. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Setting up the Development Kit 3.2. Factory Default Switch and Jumper Settings
4. Development Kit Components x
4.1. Development Kit Overview 4.2. Intel® Stratix® 10 TX FPGA 4.3. MAX® V CPLD 4.4. FPGA Configuration 4.5. Status and Setup Elements 4.6. User Input-Output Components 4.7. Clocks 4.8. Transceiver Channels 4.9. Communication Ports 4.10. Flash Memory 4.11. System Power
4.4. FPGA Configuration x
4.4.1. Configuring the FPGA over Embedded Intel® FPGA Download Cable II 4.4.2. Configuring the FPGA through Flash Memory 4.4.3. Configuring the FPGA over External Intel® FPGA Download Cable
4.7. Clocks x
4.7.1. Transceiver Dedicated Clocks 4.7.2. General-Purpose Clocks 4.7.3. Embedded Intel® FPGA Download Cable II Clock
4.10. Flash Memory x
4.10.1. Parallel NOR Flash Memory 4.10.2. EPCQL Flash Memory
4.11. System Power x
4.11.1. Power Guidelines 4.11.2. Power Supply 4.11.3. Power Management 4.11.4. Power Distribution System 4.11.5. Thermal Limitations and Protection Guidelines
5. Board Test System x
5.1. Preparing the Development Kit 5.2. Running the Board Test System 5.3. Using the Board Test System 5.4. Simple Socket Server
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The System Info Tab 5.3.3. The GPIO Tab 5.3.4. The EPCQ Tab 5.3.5. The FMC+ Tab 5.3.6. The PAM4 Tab 5.3.7. The MXP Tab 5.3.8. The QSFPDD1x2 Tab 5.3.9. The QSFPDD2x1 Tab 5.3.10. Power Monitor 5.3.11. Clock Controller
A. Additional Information x
A.1. Add SmartVID settings in QSF file A.2. Safety and Regulatory Information A.3. Compliance and Conformity Information
A.2. Safety and Regulatory Information x
A.2.1. Safety Warnings A.2.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

4.9. Communication Ports

The Intel® Stratix® 10 TX transceiver signal integrity development kit supports a 10/100/1000 BASE-T Ethernet connection using a Marvell 88E1111 PHY device and the Intel® Triple-Speed Ethernet Megacore MAC function. The device is an auto-negotiating Ethernet PHY with an SGMII interface to the FPGA.

The Intel® Stratix® 10 GX FPGA device can communicate with the LVDS interfaces at up to 1.25 Gbps. The MAC function is provided in the FPGA for typical networking applications. The Marvell 88E1111 PHY uses 2.5 V and 1.2 V power rails and requires a 25-MHz reference clock driven from a dedicated oscillator. It interfaces to an RJ-45 connector with internal magnetics that are used for driving copper lines with Ethernet traffic.

Table 16.  Ethernet PHY Pin Assignments
Schematic Signal Name Marvell 88E1111 (U23) PHY Pin Number Description
ENET_LED_LINK1000 60/73 1000 Mb link LED
ENET_LED_LINK100 74 100 Mb link LED
ENET_LED_LINK10 59/76 10 Mb link LED
ENET_LED_TX 68 TX data active LED
ENET_LED_RX 69 RX data active LED
ENET_SGMII_TX_P 82 SGMII transmit
ENET_SGMII_TX_N 81 SGMII transmit
ENET_SGMII_RX_P 77 SGMII receive
ENET_SGMII_RX_N 75 SGMII receive
ENET_XTAL_25MHZ 55 25 MHz clock
ENET_T_INTn 23 Management bus interrrupt
ENET_RSET 30 Device reset
MDIO_T 24 Management bus data input/output
MDC_T 25 Management bus data clock
MDI_P0 29 Management bus data
MDI_N0 31 Management bus data
MDI_P1 33 Management bus data
MDI_N1 34 Management bus data
MDI_P2 39 Management bus data
MDI_N2 41 Management bus data
MDI_P3 42 Management bus data
MDI_N3 43 Management bus data
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