Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit User Guide

Download PDF
ID 683591
Date 9/27/2019
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Kit
2. Getting Started x
2.1. About the Intel® Quartus® Prime Software 2.2. Development Kit Package 2.3. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Setting up the Development Kit 3.2. Factory Default Switch and Jumper Settings
4. Development Kit Components x
4.1. Development Kit Overview 4.2. Intel® Stratix® 10 TX FPGA 4.3. MAX® V CPLD 4.4. FPGA Configuration 4.5. Status and Setup Elements 4.6. User Input-Output Components 4.7. Clocks 4.8. Transceiver Channels 4.9. Communication Ports 4.10. Flash Memory 4.11. System Power
4.4. FPGA Configuration x
4.4.1. Configuring the FPGA over Embedded Intel® FPGA Download Cable II 4.4.2. Configuring the FPGA through Flash Memory 4.4.3. Configuring the FPGA over External Intel® FPGA Download Cable
4.7. Clocks x
4.7.1. Transceiver Dedicated Clocks 4.7.2. General-Purpose Clocks 4.7.3. Embedded Intel® FPGA Download Cable II Clock
4.10. Flash Memory x
4.10.1. Parallel NOR Flash Memory 4.10.2. EPCQL Flash Memory
4.11. System Power x
4.11.1. Power Guidelines 4.11.2. Power Supply 4.11.3. Power Management 4.11.4. Power Distribution System 4.11.5. Thermal Limitations and Protection Guidelines
5. Board Test System x
5.1. Preparing the Development Kit 5.2. Running the Board Test System 5.3. Using the Board Test System 5.4. Simple Socket Server
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The System Info Tab 5.3.3. The GPIO Tab 5.3.4. The EPCQ Tab 5.3.5. The FMC+ Tab 5.3.6. The PAM4 Tab 5.3.7. The MXP Tab 5.3.8. The QSFPDD1x2 Tab 5.3.9. The QSFPDD2x1 Tab 5.3.10. Power Monitor 5.3.11. Clock Controller
A. Additional Information x
A.1. Add SmartVID settings in QSF file A.2. Safety and Regulatory Information A.3. Compliance and Conformity Information
A.2. Safety and Regulatory Information x
A.2.1. Safety Warnings A.2.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

4.4.2. Configuring the FPGA through Flash Memory

The figure below shows a detailed schematic block diagram for the MAX® V + Flash AvSTx16 mode configuration implementation.
Note: Typical JTAG clock frequency for CFI Flash programming via PFL II core is 16 MHz. You may try it with a lower frequency such as 6 MHz if it fails with 16 MHz.
Figure 5. MAX V Configuration Block Diagram

The PGMSEL dipswitch (S5) is provided to select between POF files (FACTORY and USER) stored on the Flash.

The Parallel Flash Loader II (PFL II) Megafunction is used to implement the AvSTx16 configuration in the MAX® V CPLD. The PFL II Megafunction reads data from the flash and converts it to AvST format. This data is written into the Intel® Stratix® 10 TX FPGA device through dedicated AvST CLK and FPGA Config Data [15:0] pins at corresponding clock rate, such as 25 MHz, 50 MHz and 100 MHz.

Implementation will be done using an MAX® V 5M2210ZF256FBGA CPLD acting as the AvST download controller and two 1G Flash devices.

If AvST configuration mode is selected, after a POWER-ON or RESET (reconfiguration) event, the MAX® V device shall configure the Intel® Stratix® 10 TX FPGA in the AvST x16 mode with either the FACTORY POF or an USER DEFINED POF depnding on the FACTORY_LOAD setting.

The MSEL[2:0] pins indicate which configuration scheme is chosen. The manufacturing default condition is [001] for Fast AS x4 scheme.

For different configuration modes, MSEL [2:0] signals must be set acccording to the table below:
Table 6.  Support Configuration Modes for Stratix 10 TX Transceiver Signal Integrity
Configuration Scheme MSEL [2:0]
Avalon-ST (x16) 101
AS (Normal mode) 011
AS (Fast) 001
JTAG only 111
Not supported Other Settings
Level Two Title