AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA E-Tile JESD204C RX IP

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ID 683537
Date 11/30/2024
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Document Table of Contents
Document Table of Contents x
1. Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP
1. Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP x
1.1. ADC to Intel Agilex® 7 Dual Link Design Overview 1.2. ADC to Intel Agilex® 7 Dual Link Design Implementation Guidelines 1.3. Synchronized ADC to Intel Agilex® 7 Dual Link 1.4. Downloading and Operating the Design Example 1.5. Document Revision History for AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP
1.3. Synchronized ADC to Intel Agilex® 7 Dual Link x
1.3.1. Design Simulation Guidelines 1.3.2. Design Synthesis Guidelines
1.3.1. Design Simulation Guidelines x
1.3.1.1. Editing Design Example Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.2. Editing Design Example Top-Level HDL for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.3. Editing TX Simulation Model Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.4. Editing TX Simulation Model Top-Level HDL for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.5. Editing Simulation Testbench for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.6. Adding IP Signals to the Simulation Waveform 1.3.1.7. Updating the Simulation Script 1.3.1.8. Simulating the Dual Link Design 1.3.1.9. Viewing the Simulation Results
1.3.2. Design Synthesis Guidelines x
1.3.2.1. Editing Design Example Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.2.2. Editing Design Example Top-Level HDL for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.2.3. Editing Design Example Top-Level SDC Constraint for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.2.4. Compiling the Design in Quartus® Prime Software
1. Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP

1.3.1.9. Viewing the Simulation Results

The simulation testbench prints the results at the transcript or terminal where you execute the simulation script. The following example shows the printout and waveform of the simulation in the ModelSim‐ Intel® FPGA Edition:

If the simulation passes, the transcript section prints TESTBENCH_PASSED: SIM PASSED! as shown in the following figure.

Figure 11. ModelSim‐ Intel® FPGA Edition Simulation Results Transcript

If the simulation fails, the transcript section prints TESTBENCH_FAILED: SIM FAILED! along with the failure reason.

If you want to view the waveform, the following events occur during link initialization.

  1. After the /tb_top/ninit_done and global reset are deasserted, the reset sequencer deasserts the resets of the TX and RX transceivers in both Link 0 and Link 1 of the JESD204C Intel® FPGA IPs.
  2. /tb_top/tx_ready is asserted when the TX transceiver channels of Link 0 and 1 are ready.
  3. The link reset for TX JESD204C IPs, /tb_top/tx_rst_n, is deasserted when the core IO PLL is locked and intel_jesd204c/tx_pma_ready and intel_jesd204c/tx_ready are asserted.
  4. When TX channels send data to the RX channels, the RX transceiver channels ready signal, /tb_top/rx_ready, is not asserted. The link reset for the RX JESD204C IPs, /tb_top/rx_rst_n, is asserted.
    Figure 12. ModelSim‐ Intel® FPGA Edition Simulation Waveform After Global Reset Deassertion
  5. When the RX transceiver channels successfully recover the data and clock, /tb_top/rx_ready is asserted.
  6. The link reset for the RX JESD204C IPs, the /tb_top/rx_rst_n, is deasserted when the core IO PLL is locked and the intel_jesd204c/rx_pma_ready and intel_jesd204c/rx_ready are asserted.
    Figure 13. ModelSim‐ Intel® FPGA Edition Simulation Waveform when RX Transceiver Channels are Ready
  7. The RX transport layer is out of reset when the /tb_top/rx_rst_n is deasserted. The RX transport layer asserts the j204c_rx_avst_ready signal to the JESD204C Intel® FPGA IP.
  8. The RX JESD204C IPs achieve sync header alignment (j204c_rx_sh_lock is asserted) when 64 consecutive valid sync headers are detected.
  9. The RX JESD204C IPs achieve extended multiblock alignment (j204c_rx_emb_lock is asserted) when 4 consecutive valid sequences are detected. A valid sequence is defined as correct EoEMB and EoMB values for a full E*32-bit sync transition stream.
  10. j204c_rx_alldev_lane_align is asserted when both RX JESD204C IPs achieve lane alignment.
  11. j204c_rx_avst_valid is asserted when the RX transport layer streams user data to the application layer together with the start-of-multiblock (j204c_rx_somb) and start-of-extended-multiblock (j204c_rx_soemb) markers.
  12. The command channel of the RX JESD204C IP outputs the CRC-12 signal in the sync header stream. No CRC error (j204c_rx_crc_err) is detected. No parity error (j204c_rx_cmd_par_err) is detected at the command channel.
    Figure 14. ModelSim‐ Intel® FPGA Edition Simulation Waveform for Successful Link Initialization
    Figure 15. ModelSim‐ Intel® FPGA Edition Simulation Waveform for No Data Error
  13. The pattern checker checks the received sample data from the RX transport layer. No error (/tb_top/data_error) is detected.
  14. The pattern checker checks the received sync header from the RX JESD204C IP. No error (/tb_top/cmd_data_error) is detected.
  15. No TX and RX link errors or interrupts (/tb_top/tx_link_error and /tb_top/rx_link_error) are being asserted by both TX and RX JESD204C IPs. The testbench asserts the test_passed flag.
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