AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA E-Tile JESD204C RX IP

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ID 683537
Date 11/30/2024
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Document Table of Contents
Document Table of Contents x
1. Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP
1. Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP x
1.1. ADC to Intel Agilex® 7 Dual Link Design Overview 1.2. ADC to Intel Agilex® 7 Dual Link Design Implementation Guidelines 1.3. Synchronized ADC to Intel Agilex® 7 Dual Link 1.4. Downloading and Operating the Design Example 1.5. Document Revision History for AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP
1.3. Synchronized ADC to Intel Agilex® 7 Dual Link x
1.3.1. Design Simulation Guidelines 1.3.2. Design Synthesis Guidelines
1.3.1. Design Simulation Guidelines x
1.3.1.1. Editing Design Example Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.2. Editing Design Example Top-Level HDL for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.3. Editing TX Simulation Model Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.4. Editing TX Simulation Model Top-Level HDL for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.5. Editing Simulation Testbench for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.6. Adding IP Signals to the Simulation Waveform 1.3.1.7. Updating the Simulation Script 1.3.1.8. Simulating the Dual Link Design 1.3.1.9. Viewing the Simulation Results
1.3.2. Design Synthesis Guidelines x
1.3.2.1. Editing Design Example Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.2.2. Editing Design Example Top-Level HDL for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.2.3. Editing Design Example Top-Level SDC Constraint for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.2.4. Compiling the Design in Quartus® Prime Software
1. Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP

1.2. ADC to Intel Agilex® 7 Dual Link Design Implementation Guidelines

Figure 3. Design Simulation and Synthesis Implementation Guidelines

Before you implement the design in the FPGA, you can simulate the design to verify functionality. You can migrate your simulated design for synthesis, and implement the design on the FPGA. Alternatively, you can follow the synthesis flow guidelines to create the dual link design for implementation on a FPGA, without performing the simulation.

Here are the steps required to perform simulation and synthesis:

  1. Simulation flow:
    1. Generate the single link JESD204C example design using Quartus® Prime Pro Edition software version 20.1 or later with the Synthesis and Simulation options enabled. Ensure that the Multilink mode option is enabled in the JESD204C Configuration tab.
      Note: Refer to JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide for the steps to generate the design example.
    2. Simulate the design, and confirm that the functionality meets your expectations.

      The testbench prints the status of the simulation results.

    3. Modify the RX Platform Designer system to include the additional JESD204C Intel® FPGA IPs needed to form the dual link.
    4. Modify the RX top-level module to adjust the reset signal connections and to connect the additional JESD204C Intel® FPGA IPs needed for the pattern checkers.
    5. Modify the link partner TX Platform Designer system to include the additional JESD204C Intel® FPGA IPs needed to form the dual link.
    6. Modify the link partner TX top-level module to adjust the reset signal connections and to connect the additional JESD204C Intel® FPGA IPs to the pattern generators.
    7. Modify the testbench to include additional links.
    8. Optionally, you can add signals to the simulation waveform for all links of the dual link design.
    9. Update the simulation script.
    10. Elaborate and simulate the dual link design.
    11. Review the simulation results.
    Note: Perform steps 2d to 2f only if you migrate your simulated design for synthesis and implement the design on the FPGA to interface with the ADC.
  2. Synthesis flow:
    1. Generate the single link JESD204C example design using the Quartus® Prime Pro Edition software version 20.1 or later with the Synthesis and Simulation options enabled. Ensure that the Multilink mode option is enabled in the JESD204C Configuration tab.
    2. Modify the RX Platform Designer system to include the JESD204C Intel® FPGA IPs needed to form the dual link.
    3. Modify the RX top-level module to adjust the reset signals connections and to connect the JESD204C Intel® FPGA IPs needed to the pattern checkers.
    4. Perform pin assignment in the Quartus® Prime Pro Edition assignment editor.
    5. Modify the timing constraint SDC file to include the additional link or links.
    6. Compile the design in the Quartus® Prime Pro Edition software.
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