AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA E-Tile JESD204C RX IP

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ID 683537
Date 11/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP
1. Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP x
1.1. ADC to Intel Agilex® 7 Dual Link Design Overview 1.2. ADC to Intel Agilex® 7 Dual Link Design Implementation Guidelines 1.3. Synchronized ADC to Intel Agilex® 7 Dual Link 1.4. Downloading and Operating the Design Example 1.5. Document Revision History for AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP
1.3. Synchronized ADC to Intel Agilex® 7 Dual Link x
1.3.1. Design Simulation Guidelines 1.3.2. Design Synthesis Guidelines
1.3.1. Design Simulation Guidelines x
1.3.1.1. Editing Design Example Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.2. Editing Design Example Top-Level HDL for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.3. Editing TX Simulation Model Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.4. Editing TX Simulation Model Top-Level HDL for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.5. Editing Simulation Testbench for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.6. Adding IP Signals to the Simulation Waveform 1.3.1.7. Updating the Simulation Script 1.3.1.8. Simulating the Dual Link Design 1.3.1.9. Viewing the Simulation Results
1.3.2. Design Synthesis Guidelines x
1.3.2.1. Editing Design Example Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.2.2. Editing Design Example Top-Level HDL for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.2.3. Editing Design Example Top-Level SDC Constraint for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.2.4. Compiling the Design in Quartus® Prime Software
1. Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP

1.3.1.7. Updating the Simulation Script

Because of the additional JESD204C Intel® FPGA IPs and connection changes in the Platform Designer system, some of the generated Platform Designer filenames are changed. This includes filenames of components within the Platform Designer interconnect. You may encounter the following elaboration error, for example, in Modelsim: 

# ** Note: (vsim-3812) Design is being optimized...
# ** Error: ../../ed/rtl/rx/j204c_rx_ss/sim/j204c_rx_ss.v(569): Module 'j204c_rx_ss_altera_mm_interconnect_191_gpcal4y' is not defined.
# ** Error: ../../ed/rtl/rx/j204c_rx_ss/sim/j204c_rx_ss.v(599): Module 'j204c_rx_ss_altera_mm_interconnect_191_5wgszea' is not defined.
# ** Error: ../models/j204c_tx/j204c_tx_ss/sim/j204c_tx_ss.v(544): Module 'j204c_tx_ss_altera_mm_interconnect_191_lwybday' is not defined.
# ** Error: ../models/j204c_tx/j204c_tx_ss/sim/j204c_tx_ss.v(574): Module 'j204c_tx_ss_altera_mm_interconnect_191_syluiea' is not defined.
# Optimization failed
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./modelsim_sim.tcl PAUSED at line 28

Follow these steps to update the simulation script due to changes in the Platform Designer interconnect components:

  1. The TCL simulation script for each simulator is located in simulation/setup_scripts/common folder. Open the simulation script of the simulator of your choice.
  2. Based on the error messages, locate the impacted Platform Designer interconnect component files in ed/rtl/rx/j204c_rx_ss/altera_mm_interconnect_1920/sim and simulation/models/j204c_tx/j204c_tx_ss/altera_mm_interconnect_1920/sim folders.
  3. Edit the simulation script to update the random string suffix of the Platform Designer interconnect components. Example of altera_mm_interconnect:
    • Update j204c_rx_ss_altera_mm_interconnect_1920_ lf2qeua .v to j204c_rx_ss_altera_mm_interconnect_1920_ kkuhzua .v
    • Update j204c_rx_ss_altera_mm_interconnect_1920_ nowcoqy .v to j204c_rx_ss_altera_mm_interconnect_1920_ y7egswi .v
    • Update j204c_tx_ss_altera_mm_interconnect_1920_ qfllbpq .v to j204c_tx_ss_altera_mm_interconnect_1920_ fsezvgq .v
    • Update j204c_tx_ss_altera_mm_interconnect_1920_ mgx3bmy .v to j204c_tx_ss_altera_mm_interconnect_1920_ csopxfa .v
  4. Add entries in the simulation script to resolve all the elaboration errors related to the interconnect components of both RX and TX Platform Designer systems. Examples of the components include:
    • altera_merlin_router
    • altera_merlin_burst_adapter
    • altera_merlin_demultiplexer
    • altera_merlin_multiplexer
    • altera_merlin_width_adapter
    • altera_merlin_traffic_limiter_altera_avalon_sc_fifo
    • altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage
  5. Save the simulation script changes.
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