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1.1. ADC to Intel Agilex® 7 Dual Link Design Overview
1.2. ADC to Intel Agilex® 7 Dual Link Design Implementation Guidelines
1.3. Synchronized ADC to Intel Agilex® 7 Dual Link
1.4. Downloading and Operating the Design Example
1.5. Document Revision History for AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP
1.3.1.1. Editing Design Example Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link
1.3.1.2. Editing Design Example Top-Level HDL for Synchronized ADC to Intel Agilex® 7 Dual Link
1.3.1.3. Editing TX Simulation Model Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link
1.3.1.4. Editing TX Simulation Model Top-Level HDL for Synchronized ADC to Intel Agilex® 7 Dual Link
1.3.1.5. Editing Simulation Testbench for Synchronized ADC to Intel Agilex® 7 Dual Link
1.3.1.6. Adding IP Signals to the Simulation Waveform
1.3.1.7. Updating the Simulation Script
1.3.1.8. Simulating the Dual Link Design
1.3.1.9. Viewing the Simulation Results
1.3.2.1. Editing Design Example Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link
1.3.2.2. Editing Design Example Top-Level HDL for Synchronized ADC to Intel Agilex® 7 Dual Link
1.3.2.3. Editing Design Example Top-Level SDC Constraint for Synchronized ADC to Intel Agilex® 7 Dual Link
1.3.2.4. Compiling the Design in Quartus® Prime Software
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1.3.1. Design Simulation Guidelines
When the JESD204C RX design example is generated, the JESD204C TX FPGA IP is used to represent the ADC in the simulation testbench.
Figure 6. Simulation Testbench Block Diagram
The steps in the following sections guide you to add RX and TX IPs into the respective RX and TX subsystems.
Section Content
Editing Design Example Platform Designer System for Synchronized ADC to Intel Agilex 7 Dual Link
Editing Design Example Top-Level HDL for Synchronized ADC to Intel Agilex 7 Dual Link
Editing TX Simulation Model Platform Designer System for Synchronized ADC to Intel Agilex 7 Dual Link
Editing TX Simulation Model Top-Level HDL for Synchronized ADC to Intel Agilex 7 Dual Link
Editing Simulation Testbench for Synchronized ADC to Intel Agilex 7 Dual Link
Adding IP Signals to the Simulation Waveform
Updating the Simulation Script
Simulating the Dual Link Design
Viewing the Simulation Results