AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA E-Tile JESD204C RX IP

Download PDF
ID 683537
Date 11/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP
1. Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP x
1.1. ADC to Intel Agilex® 7 Dual Link Design Overview 1.2. ADC to Intel Agilex® 7 Dual Link Design Implementation Guidelines 1.3. Synchronized ADC to Intel Agilex® 7 Dual Link 1.4. Downloading and Operating the Design Example 1.5. Document Revision History for AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP
1.3. Synchronized ADC to Intel Agilex® 7 Dual Link x
1.3.1. Design Simulation Guidelines 1.3.2. Design Synthesis Guidelines
1.3.1. Design Simulation Guidelines x
1.3.1.1. Editing Design Example Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.2. Editing Design Example Top-Level HDL for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.3. Editing TX Simulation Model Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.4. Editing TX Simulation Model Top-Level HDL for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.5. Editing Simulation Testbench for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.6. Adding IP Signals to the Simulation Waveform 1.3.1.7. Updating the Simulation Script 1.3.1.8. Simulating the Dual Link Design 1.3.1.9. Viewing the Simulation Results
1.3.2. Design Synthesis Guidelines x
1.3.2.1. Editing Design Example Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.2.2. Editing Design Example Top-Level HDL for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.2.3. Editing Design Example Top-Level SDC Constraint for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.2.4. Compiling the Design in Quartus® Prime Software
1. Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP

1.3.2.3. Editing Design Example Top-Level SDC Constraint for Synchronized ADC to Intel Agilex® 7 Dual Link

Several modifications to the top-level SDC constraint, intel_j204c_ed_rx.sdc, are needed to ensure that the newly added IPs are fully constrained:

  1. In the set_clock_groups constraints, add entries for the newly added IPs. 
    set_clock_groups -asynchronous -group {mgmt_clk} \
-group {ALTERA_INSERTED_INTOSC_FOR_TRS|divided_osc_clk} \
-group {u_j204c_rx_ss|core_pll|core_pll_clk_1x u_j204c_rx_ss|core_pll|core_pll_clk_2x u_j204c_rx_ss|core_pll|core_pll_refclk } \
-group {u_j204c_rx_ss|j204c_rx_ip|<ip core instance name>|intel_jesd204c|j204c_rx_phy_hip_inst|j204c_rx_hip_inst|inst_xcvr|rx_clkout|ch0} \
-group {u_j204c_rx_ss|j204c_rx_ip|<ip core instance name>|intel_jesd204c|j204c_rx_phy_hip_inst|j204c_rx_hip_inst|inst_xcvr|rx_clkout|ch1} \
-group {u_j204c_rx_ss|j204c_rx_ip|<ip core instance name>|intel_jesd204c|j204c_rx_phy_hip_inst|j204c_rx_hip_inst|inst_xcvr|rx_clkout|ch2} \
-group {u_j204c_rx_ss|j204c_rx_ip|<ip core instance name>|intel_jesd204c|j204c_rx_phy_hip_inst|j204c_rx_hip_inst|inst_xcvr|rx_clkout|ch3} \
-group {altera_reserved_tck}

set_clock_groups -async -group {u_j204c_rx_ss|j204c_rx_ip|<ip core instance name>|intel_jesd204c|j204c_rx_phy_hip_inst|j204c_rx_hip_inst|inst_xcvr|rx_transfer_clk|ch0} \
-group {u_j204c_rx_ss|j204c_rx_ip|<ip core instance name>|intel_jesd204c|j204c_rx_phy_hip_inst|j204c_rx_hip_inst|inst_xcvr|rx_transfer_clk|ch1} \
-group {u_j204c_rx_ss|j204c_rx_ip|<ip core instance name>|intel_jesd204c|j204c_rx_phy_hip_inst|j204c_rx_hip_inst|inst_xcvr|rx_transfer_clk|ch2} \
-group {u_j204c_rx_ss|j204c_rx_ip|<ip core instance name>|intel_jesd204c|j204c_rx_phy_hip_inst|j204c_rx_hip_inst|inst_xcvr|rx_transfer_clk|ch3} \
-group {u_j204c_rx_ss|core_pll|core_pll_clk_1x u_j204c_rx_ss|core_pll|core_pll_clk_2x } \
-group {mgmt_clk}

    <ip core instance name> is the name for the duplicated copy of the JESD204C Intel® FPGA IP that you named in step 4.

    The following example has the newly added design entities: 
    -group {u_j204c_rx_ss|j204c_rx_ip|intel_jesd204c_1|intel_jesd204c|j204c_rx_phy_hip_inst|j204c_rx_hip_inst|inst_xcvr|rx_clkout|ch0} \
    -group {u_j204c_rx_ss|j204c_rx_ip|intel_jesd204c_1|intel_jesd204c|j204c_rx_phy_hip_inst|j204c_rx_hip_inst|inst_xcvr|rx_transfer_clk|ch0} \
  2. Edit the set_multicycle_path constraint by changing the index of the reset synchronizer data register from 0 to 1 (in other words, dreg[1]). Change the top level Platform Designer system instance name from u_j204c_rx_tx_ss to u_j204c_rx_ss: 
    set_multicycle_path -setup -from reset_synchronizer|u|dreg[1] -to u_j204c_rx_ss|core_pll|core_pll|tennm_pll~pll_ctrl_reg 2

set_multicycle_path -hold -from reset_synchronizer|u|dreg[1] -to u_j204c_rx_ss|core_pll|core_pll|tennm_pll~pll_ctrl_reg 1
Level Two Title