AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP

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ID 683537
Date 3/26/2023
Public
Document Table of Contents
Document Table of Contents x
1. Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP
1. Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP x
1.1. ADC to Intel Agilex® 7 Dual Link Design Overview 1.2. ADC to Intel Agilex® 7 Dual Link Design Implementation Guidelines 1.3. Synchronized ADC to Intel Agilex® 7 Dual Link 1.4. Downloading and Operating the Design Example 1.5. Document Revision History for AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP
1.3. Synchronized ADC to Intel Agilex® 7 Dual Link x
1.3.1. Design Simulation Guidelines 1.3.2. Design Synthesis Guidelines
1.3.1. Design Simulation Guidelines x
1.3.1.1. Editing Design Example Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.2. Editing Design Example Top-Level HDL for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.3. Editing TX Simulation Model Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.4. Editing TX Simulation Model Top-Level HDL for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.5. Editing Simulation Testbench for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.6. Adding IP Signals to the Simulation Waveform 1.3.1.7. Updating the Simulation Script 1.3.1.8. Simulating the Dual Link Design 1.3.1.9. Viewing the Simulation Results
1.3.2. Design Synthesis Guidelines x
1.3.2.1. Editing Design Example Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.2.2. Editing Design Example Top-Level HDL for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.2.3. Editing Design Example Top-Level SDC Constraint for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.2.4. Compiling the Design in Intel® Quartus® Prime Software
1. Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP

1.3.1.4. Editing TX Simulation Model Top-Level HDL for Synchronized ADC to Intel Agilex® 7 Dual Link

The generate statement in the Verilog HDL file uses the LINK system parameter as an index variable to generate the requisite number of instances for the dual llink use case.
  1. Open the top-level HDL file (intel_j204c_ed_tx.sv) in a text editor.
  2. Modify the LINK system parameter to reflect the number of links in your design.
  3. Insert the newly exported ports from the Platform Designer at the Platform Designer instantiation.
  4. To make the connections for the Platform Designer ports:
    1. For TX link reset and frame reset, distribute the tx_rst[0] wire from the reset sequencer in Platform Designer to the IPs and pattern generators of the second and subsequent links. One way to achieve this is to hard code the index in the tx_rst[i] wire in the pattern generator and the synchronizer (j204c_pulse_CDC) instantiations generation loop with tx_rst[0].
    2. Create the following wires:
      1. tx_pma_ready_in_all
      2. tx_xcvr_ready_in_all
    3. Connect the tx_pma_ready_in of each link to the input of an AND gate. Connect the output of the AND gate to tx_pma_ready_in_all. 
      // Example in Verilog
assign tx_pma_ready_in_all = &tx_pma_ready_in;
    4. Connect the tx_xcvr_ready_in of each link to the input of an AND gate. Connect the output of the AND gate to tx_xcvr_ready_in_all. 
      // Example in Verilog
assign tx_xcvr_ready_in_all = &tx_xcvr_ready_in;
    5. Replace the tx_pma_ready_in[0] connection at the rst_seq_0_reset3_dsrt_qual_reset3_dsrt_qual port of the Platform Designer system with the output of the AND gate of tx_pma_ready_in_all.
    6. Replace the tx_xcvr_ready_in[0] connection at the rst_seq_0_reset4_dsrt_qual_reset4_dsrt_qual port of the Platform Designer system with the output of the AND gate of tx_xcvr_ready_in_all.
    7. For the rest of the ports, increase the index wires from 0 to 1, and use subsequent numbers for the subsequent links.
      Example: tx_avst_data[1] wire should be connected to link 1 IP.
  5. Save the top-level HDL file changes.
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