AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA E-Tile JESD204C RX IP

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ID 683537
Date 11/30/2024
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Document Table of Contents
Document Table of Contents x
1. Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP
1. Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP x
1.1. ADC to Intel Agilex® 7 Dual Link Design Overview 1.2. ADC to Intel Agilex® 7 Dual Link Design Implementation Guidelines 1.3. Synchronized ADC to Intel Agilex® 7 Dual Link 1.4. Downloading and Operating the Design Example 1.5. Document Revision History for AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP
1.3. Synchronized ADC to Intel Agilex® 7 Dual Link x
1.3.1. Design Simulation Guidelines 1.3.2. Design Synthesis Guidelines
1.3.1. Design Simulation Guidelines x
1.3.1.1. Editing Design Example Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.2. Editing Design Example Top-Level HDL for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.3. Editing TX Simulation Model Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.4. Editing TX Simulation Model Top-Level HDL for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.5. Editing Simulation Testbench for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.6. Adding IP Signals to the Simulation Waveform 1.3.1.7. Updating the Simulation Script 1.3.1.8. Simulating the Dual Link Design 1.3.1.9. Viewing the Simulation Results
1.3.2. Design Synthesis Guidelines x
1.3.2.1. Editing Design Example Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.2.2. Editing Design Example Top-Level HDL for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.2.3. Editing Design Example Top-Level SDC Constraint for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.2.4. Compiling the Design in Quartus® Prime Software
1. Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP

1.3.1.1. Editing Design Example Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link

  1. Open the Quartus® Prime project of the generated design example, intel_j204c_ed_rx.qpf, in the ed/quartus/ folder.
  2. Open the top-level system, j204c_rx_ss.qsys, in Platform Designer. The RX .qsys file is located in the ed/rtl/rx/ folder.
  3. In the System View tab, right-click the j204c_rx_ip instance and select Drill into Subsystem. This opens the j204c_rx_ip Platform Designer subsystem.
  4. Right-click the intel_jesd204c component and select Duplicate.
    This duplicates the JESD204C Intel® FPGA IP. Rename the duplicated IP as intel_jesd204c_1.
    Note: Select No if the Platform Designer prompts the following: Do you want to also duplicate the IP Variant file on the disk? This is because the duplicated JESD204C Intel® FPGA IP has the same parameters as the original JESD204C Intel® FPGA IP .
  5. Double click at the export column to export all the JESD204C Intel® FPGA IP ports except for the j204c_tx2rx_lbdata port.
  6. Move up one level of the hierarchy to j204c_rx_ss; this is the top level of the Platform Designer system.
  7. Connect the duplicated IP port as shown in the following table.
    Ports for Duplicated IP Connection
    j204c_rx_phy_rst_n rst_seq_1.reset_out0
    j204c_pll_refclk refclk_xcvr.out_clk 1
    j204c_reconfig_clk mgmt_clk.out_clk
    j204c_reconfig_reset reset_controller_0.reset_out
    j204c_reconfig

    jtag_avmm_bridge.master

    j204c_rx_avs_clk mgmt_clk.out_clk
    j204c_rx_avs_rst_n rst_seq_1.reset_out0
    j204c_rx_avs mm_bridge.m0
    j204c_rxlink_clk ed_control.rxlink_clk
    j204c_rxframe_clk rxframe_clk.out_clk
  8. Change the connection of the j204c_rx_avs_rst_n port of the original JESD204C IP to rst_seq_1.reset_out0.
    Note: You can assert the Avalon® memory-mapped interface reset for the IP control and status register (CSR) at the same time as the PHY reset. Refer to the JESD204C TX/RX Reset Sequence figure in the JESD204C Intel® FPGA IP User Guide.
  9. Export the rest of the ports by clicking on the Double-click to export in the Export column of the System View tab.
  10. At the address map, adjust the starting address of j204c_rx_avs and j204c_reconfig interfaces so that there is no conflict with other components or interfaces. For example, you can set the starting address of the intel_jesd204c_1 IP to 0x000d_0400 as shown in the following table.
    Table 2.  Synchronized ADC-FPGA Dual Link Address Map for Design Example with System Console Control
      jtag_avmm_bridge.master mm_bridge.m0
    j204c_rx_ip.intel_jesd204c_j204c_rx_avs N/A 0x000d_0000 – 0x000d_03ff
    j204c_rx_ip.intel_jesd204c_1_j204c_rx_avs N/A 0x000d_0400 – 0x000d_07ff
    j204c_rx_ip.intel_jesd204c_j204c_reconfig 0x0200_0000 – 0x021f_ffff 2 N/A
    j204c_rx_ip.intel_jesd204c_1_j204c_reconfig 0x0220_0000 – 0x023f_ffff 2 N/A
  11. Repeat step 4 through step 10 for subsequent links in your design. Refer to the following figure for the screenshot of link 1 of the JESD204C IP.
  12. Click Generate HDL to generate the design files needed for Quartus® Prime compilation.
    1. Ensure that you select the HDL language of your choice in the Simulation section of the Generation window to generate the simulation models.
    2. Click Generate and Yes to save and generate the design files needed for simulation.
  13. After the HDL generation is completed, select Generate from the menu of the Platform Designer. Select Show Instantiation Template…, and click Copy.
  14. Paste the instantiation template of j204c_rx_ss Platform Designer into a text editor.
    You must update the instantiated Platform Designer ports at the top-level HDL.
  15. Click Finish to save your Platform Designer settings, and exit the Platform Designer window.
Related Information
1 You cannot share the same transceiver reference clock pin for transceiver channels located in different transceiver tiles. For this case, you should instantiate multiple refclk_xcvr clock sources in Platform Designer and connect them to the transceiver reference clock pins in different transceiver tiles.
2 The address span of the PHY reconfiguration interface depends on the number of transceiver channels.
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