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1.1. ADC to Intel Agilex® 7 Dual Link Design Overview
1.2. ADC to Intel Agilex® 7 Dual Link Design Implementation Guidelines
1.3. Synchronized ADC to Intel Agilex® 7 Dual Link
1.4. Downloading and Operating the Design Example
1.5. Document Revision History for AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP
1.3.1.1. Editing Design Example Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link
1.3.1.2. Editing Design Example Top-Level HDL for Synchronized ADC to Intel Agilex® 7 Dual Link
1.3.1.3. Editing TX Simulation Model Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link
1.3.1.4. Editing TX Simulation Model Top-Level HDL for Synchronized ADC to Intel Agilex® 7 Dual Link
1.3.1.5. Editing Simulation Testbench for Synchronized ADC to Intel Agilex® 7 Dual Link
1.3.1.6. Adding IP Signals to the Simulation Waveform
1.3.1.7. Updating the Simulation Script
1.3.1.8. Simulating the Dual Link Design
1.3.1.9. Viewing the Simulation Results
1.3.2.1. Editing Design Example Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link
1.3.2.2. Editing Design Example Top-Level HDL for Synchronized ADC to Intel Agilex® 7 Dual Link
1.3.2.3. Editing Design Example Top-Level SDC Constraint for Synchronized ADC to Intel Agilex® 7 Dual Link
1.3.2.4. Compiling the Design in Quartus® Prime Software
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1.1. ADC to Intel Agilex® 7 Dual Link Design Overview
The design example Platform Designer system and top-level HDL file are designed for easy implementation of a JESD204C dual link use case. In the top-level HDL file, each link in a JESD204C link use case corresponds to an instantiation of a JESD204C Intel® FPGA IP and a pattern checker. The dual link design is created by adding multiple JESD204C Intel® FPGA IPs and pattern checkers to a single link design example. The LINK parameter at the top-level HDL generates multiple pattern checkers. You must duplicate JESD204C Intel® FPGA IPs in the Platform Designer and make connections to the pattern checkers. For a synchronized dual link, AND gates are used to combine the alignment signals.
Figure 2. Platform Designer System of the Single Link Design Example
The j204c_rx_ip subsystem in the design example contains one RX IP to interface with one ADC. To interface with multiple synchronized converters, the j204c_rx_ip should contain multiple IPs.