AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA E-Tile JESD204C RX IP

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ID 683537
Date 11/30/2024
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Document Table of Contents
Document Table of Contents x
1. Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP
1. Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP x
1.1. ADC to Intel Agilex® 7 Dual Link Design Overview 1.2. ADC to Intel Agilex® 7 Dual Link Design Implementation Guidelines 1.3. Synchronized ADC to Intel Agilex® 7 Dual Link 1.4. Downloading and Operating the Design Example 1.5. Document Revision History for AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP
1.3. Synchronized ADC to Intel Agilex® 7 Dual Link x
1.3.1. Design Simulation Guidelines 1.3.2. Design Synthesis Guidelines
1.3.1. Design Simulation Guidelines x
1.3.1.1. Editing Design Example Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.2. Editing Design Example Top-Level HDL for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.3. Editing TX Simulation Model Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.4. Editing TX Simulation Model Top-Level HDL for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.5. Editing Simulation Testbench for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.6. Adding IP Signals to the Simulation Waveform 1.3.1.7. Updating the Simulation Script 1.3.1.8. Simulating the Dual Link Design 1.3.1.9. Viewing the Simulation Results
1.3.2. Design Synthesis Guidelines x
1.3.2.1. Editing Design Example Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.2.2. Editing Design Example Top-Level HDL for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.2.3. Editing Design Example Top-Level SDC Constraint for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.2.4. Compiling the Design in Quartus® Prime Software
1. Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP

1.3.1.3. Editing TX Simulation Model Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link

  1. Open the top-level system, j204c_tx_ss.qsys, in Platform Designer.
    1. The TX .qsys file is located in the simulation/models/j204c_tx/ folder.
    2. To open the .qsys file in Platform Designer, you must have an associated Quartus® Prime project. Copy the intel_j204c_ed_rx.qpf and intel_j204c_ed_rx.qsf files from the ed/quartus/ folder into the simulation/models/j204c_tx/ folder.
    3. Select intel_j204c_ed_rx.qpf, and click Open.
    4. When the IP Synchronization Result window opens, click OK to proceed.
  2. In the System View tab, right-click the j204c_tx_ip instance and select Drill into Subsystem. This opens the j204c_tx_ip.qsys Platform Designer subsystem.
  3. Right-click the intel_jesd204c component, and select Duplicate to duplicate the JESD204C Intel® FPGA IP. You can rename the duplicated IP as intel_jesd204c_1.
    Note: Select No if the Platform Designer prompts Do you want to also duplicate the IP Variant file on the disk? This is because the duplicated JESD204C Intel® FPGA IP has the same parameters as the original JESD204C Intel® FPGA IP.
    Note: The Multilink mode option at the JESD204C Configurations tab does not affect the number of ports for the JESD204C transmitter. Leave this option on or off.
  4. Export all JESD204C Intel® FPGA IP ports except for j204c_tx2rx_lbdata.
  5. Move up one level of the hierarchy to j204c_tx_ss, the top level of the Platform Designer System.
  6. Connect the duplicated IP port as shown in the following table:
    Ports for Duplicated IP Connection
    j204c_tx_phy_rst_n rst_seq_0.reset_out1
    j204c_pll_refclk refclk_xcvr.out_clk
    j204c_reconfig_clk mgmt_clk.out_clk
    j204c_reconfig_reset reset_controller_0.reset_out
    j204c_reconfig jtag_avmm_bridge.master
    j204c_txlink_clk ed_control.txlink_clk
    j204c_txframe_clk txframe_clk.out_clk
    j204c_tx_avs_clk mgmt_clk.out_clk
    j204c_tx_avs_rst_n rst_seq_0.reset_out1
    j204_tx_avs mm_bridge.m0
  7. Change the connection of the j204c_tx_avs_rst_n port of the original JESD204C IP to rst_seq_0.reset_out1.
    Note: You can assert the Avalon® memory-mapped interface reset for the IP control and status register (CSR) at the same time as the PHY reset. Refer to the JESD204C TX/RX Reset Sequence figure in the JESD204C Intel® FPGA IP User Guide.
  8. Export the rest of the ports to the top-level Platform Designer system. To export a port, click Double-click to export in the Export column of the System View tab.
  9. At the address map, adjust the starting address of the j204c_tx_avs and j204c_reconfig interfaces of the newly added JESD204C Intel® FPGA IP code so that there is no conflict with other components or interfaces. For example, you can set the starting address of intel_jesd204c_1 IP to 0x000c_0400 as shown in the following table:
    Table 3.  Synchronized ADC to FPGA Dual Link TX Platform Designer Simulation Model Address Map for System Console Control
      jtag_avmm_bridge.master mm_bridge.m0
    j204c_tx_ip.intel_jesd204c_j204c_tx_avs N/A 0x000c_0000 – 0x000c_03ff
    j204c_tx_ip.intel_jesd204c_1_j204c_tx_avs N/A 0x000c_0400 – 0x000c_07ff
    j204c_tx_ip.intel_jesd204c_j204c_reconfig 0x0200_0000 – 0x021f_ffff 3 N/A
    j204c_tx_ip.intel_jesd204c_1_j204c_reconfig 0x0220_0000 – 0x023f_ffff 3 N/A
  10. Repeat step 3 through step 9 for subsequent links in your design.
  11. Click Generate HDL.
  12. Ensure you select the HDL language of your choice in the Simulation section of the Generation windows to generate the simulation models.
  13. Click Generate and Yes to save and generate the design files needed for simulation.
  14. After the HDL generation is completed, select Generate from the menu, select Show Instantiation Template…, and click Copy.
  15. Paste the instantiation template of the j204c_tx_ss Platform Designer in a text editor.
    You must update the instantiated Platform Designer ports at the top-level HDL.
  16. Click Finish to save your Platform Designer settings and exit the Platform Designer window.
Related Information
3 The address span of the PHY reconfiguration interface depends on the number of transceiver channels.
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