This application note provides guidelines on how to scale up the single link of the JESD204C Intel® FPGA IP design example generated from the Quartus® Prime software to handle a dual link system. A single link in JESD204C has one or more high speed transceiver lanes or channels.
In some JESD204C applications, multiple analog-to-digital converters (ADCs) are used to sample the analog signals synchronously. Hence, synchronization between multiple converters in the array is required. In these applications, multiple converters interface with a single logic device, such as the Intel Agilex® 7 FPGA E-tile.
Before implementing the dual link design, you must generate the receiver (RX) single-link design example from the
Quartus® Prime software.
Intel® recommends that you perform an RTL simulation on this single link design example to confirm the functionality matches your expectation before transforming the design example to the dual link design. The guidelines in the following section assume the JESD204C parameters for each link in the dual link design are identical.
Figure 1. JESD204C Dual LinkFigure shows one dual link. All lanes are aligned.