AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA E-Tile JESD204C RX IP
Visible to Intel only — GUID: gtw1576570814205
Ixiasoft
Visible to Intel only — GUID: gtw1576570814205
Ixiasoft
1. Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP
In some JESD204C applications, multiple analog-to-digital converters (ADCs) are used to sample the analog signals synchronously. Hence, synchronization between multiple converters in the array is required. In these applications, multiple converters interface with a single logic device, such as the Intel Agilex® 7 FPGA E-tile.
Section Content
ADC to Intel Agilex 7 Dual Link Design Overview
ADC to Intel Agilex 7 Dual Link Design Implementation Guidelines
Synchronized ADC to Intel Agilex 7 Dual Link
Downloading and Operating the Design Example
Document Revision History for AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex 7 FPGA E-Tile JESD204C RX IP