AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA E-Tile JESD204C RX IP

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ID 683537
Date 11/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP
1. Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP x
1.1. ADC to Intel Agilex® 7 Dual Link Design Overview 1.2. ADC to Intel Agilex® 7 Dual Link Design Implementation Guidelines 1.3. Synchronized ADC to Intel Agilex® 7 Dual Link 1.4. Downloading and Operating the Design Example 1.5. Document Revision History for AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP
1.3. Synchronized ADC to Intel Agilex® 7 Dual Link x
1.3.1. Design Simulation Guidelines 1.3.2. Design Synthesis Guidelines
1.3.1. Design Simulation Guidelines x
1.3.1.1. Editing Design Example Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.2. Editing Design Example Top-Level HDL for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.3. Editing TX Simulation Model Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.4. Editing TX Simulation Model Top-Level HDL for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.5. Editing Simulation Testbench for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.1.6. Adding IP Signals to the Simulation Waveform 1.3.1.7. Updating the Simulation Script 1.3.1.8. Simulating the Dual Link Design 1.3.1.9. Viewing the Simulation Results
1.3.2. Design Synthesis Guidelines x
1.3.2.1. Editing Design Example Platform Designer System for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.2.2. Editing Design Example Top-Level HDL for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.2.3. Editing Design Example Top-Level SDC Constraint for Synchronized ADC to Intel Agilex® 7 Dual Link 1.3.2.4. Compiling the Design in Quartus® Prime Software
1. Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex® 7 FPGA E-Tile JESD204C RX IP

1.3.1.8. Simulating the Dual Link Design

After modifications to the j204c_rx_ss.qsys, j204c_rx_ip.qsys, intel_j204c_ed_rx.sv, j204c_tx_ss.qsys, j204c_tx_ip.qsys, intel_j204c_ed_tx.sv, tb_top.sv, and <simulator>_files.tcl, you are ready to simulate the dual link design using the simulator of your choice. The following example uses the ModelSim‐ Intel® FPGA Edition.

  1. Launch the ModelSim‐ Intel® FPGA Edition.
  2. From the File menu, select Change Directory.
  3. Select simulation/mentor.
  4. To run the simulation script, type the following command at the transcript prompt: 
    do modelsim_sim.tcl
    Note: Depending on your simulator, the simulation may take a few hours to complete. For the Modelsim- Intel® FPGA Edition, the simulation takes 2 to 3 hours.
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