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Release Information
LVDS SERDES Intel® FPGA IP Features
LVDS SERDES IP Core Functional Modes
LVDS SERDES IP Core Functional Description
LVDS SERDES IP Initialization and Reset
LVDS SERDES Intel® FPGA IP Signals
LVDS SERDES Intel® FPGA IP Parameter Settings
LVDS SERDES Intel® FPGA IP Timing
LVDS SERDES Intel® FPGA IP Design Examples
Additional LVDS SERDES IP Core References
LVDS SERDES Intel® FPGA IP User Guide Archives
Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
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Initializing the LVDS SERDES IP in Non-DPA Mode
The PLL is operational after it achieves lock in user mode. Before transferring data using SERDES block with the LVDS SERDES IP, ensure that the PLL is locked to the reference clock.
Intel recommends that you follow these steps to initialize the LVDS SERDES IP in non-DPA mode:
- During entry into user mode, assert the pll_areset signal for at least 10 ns.
You can also perform this step at any time in user mode operation to reset the interface.
- After at least 10 ns, deassert the pll_areset signal and monitor the pll_locked port.
After the PLL lock port asserts and becomes stable, the SERDES blocks are ready for operation.
After the initialization, you can proceed to align the word boundaries (bit slip).