Intel® Quartus® Prime Standard Edition User Guide: Partial Reconfiguration

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ID 683499
Date 9/24/2018
Public
Document Table of Contents
Document Table of Contents x
1. Design Planning for Partial Reconfiguration A. Intel® Quartus® Prime Standard Edition User Guides
1. Design Planning for Partial Reconfiguration x
1.1. Terminology 1.2. An Example of a Partial Reconfiguration Design 1.3. Partial Reconfiguration Modes 1.4. Partial Reconfiguration Design Flow 1.5. Freeze Logic for PR Regions 1.6. Implementation Details for Partial Reconfiguration 1.7. Example of a Partial Reconfiguration Design with an External Host 1.8. Example Partial Reconfiguration with an Internal Host 1.9. Partial Reconfiguration Project Management 1.10. Programming Files for a Partial Reconfiguration Project 1.11. On-Chip Debug for PR Designs 1.12. Partial Reconfiguration Known Limitations 1.13. Document Revision History
1.1. Terminology x
1.1.1. Determining Resources for Partial Reconfiguration
1.3. Partial Reconfiguration Modes x
1.3.1. SCRUB Mode 1.3.2. AND/OR Mode 1.3.3. Programming File Sizes for a Partial Reconfiguration Project
1.4. Partial Reconfiguration Design Flow x
1.4.1. Design Partitions for Partial Reconfiguration 1.4.2. Incremental Compilation Partitions for Partial Reconfiguration 1.4.3. Partial Reconfiguration Controller Instantiation in the Design 1.4.4. Wrapper Logic for PR Regions
1.4.3. Partial Reconfiguration Controller Instantiation in the Design x
1.4.3.1. Component Declaration of the PR Control Block and CRC Block in VHDL 1.4.3.2. Instantiating the PR Control Block and CRC Block in VHDL 1.4.3.3. Instantiating the PR Control Block and CRC Block in Verilog HDL
1.5. Freeze Logic for PR Regions x
1.5.1. Clocks and Other Global Signals for a PR Design 1.5.2. Floorplan Assignments for PR Designs
1.6. Implementation Details for Partial Reconfiguration x
1.6.1. Interface with the PR Control Block through a PR Host 1.6.2. Partial Reconfiguration Pins 1.6.3. PR Control Signals Interface 1.6.4. Reconfiguring a PR Region 1.6.5. Partial Reconfiguration Cycle Waveform
1.7. Example of a Partial Reconfiguration Design with an External Host x
1.7.1. Example of Using an External Host with Multiple Devices
1.9. Partial Reconfiguration Project Management x
1.9.1. Create Reconfigurable Revisions 1.9.2. Compiling Reconfigurable Revisions 1.9.3. Timing Closure for a Partial Reconfiguration Project 1.9.4. PR Bitstream Compression and Encryption ( Intel® Arria® 10 Designs)
1.10. Programming Files for a Partial Reconfiguration Project x
1.10.1. Generating Required Programming Files 1.10.2. Generate PR Programming Files with the Convert Programming Files Dialog Box
1.10.2. Generate PR Programming Files with the Convert Programming Files Dialog Box x
1.10.2.1. Generating a .pmsf File from a .msf and .sof Input File 1.10.2.2. Generating a .rbf File from a .pmsf Input File 1.10.2.3. Create a Merged .msf File from Multiple .msf Files 1.10.2.4. Generating a Merged .pmsf File from Multiple .pmsf Files 1.10.2.5. Enable Partial Reconfiguration Bitstream Decompression when Configuring Base Design SOF file in JTAG mode 1.10.2.6. Enable Bitstream Decryption Option
1.12. Partial Reconfiguration Known Limitations x
1.12.1. Memory Blocks Initialization Requirement for PR Designs 1.12.2. M20K RAM Blocks in PR Designs 1.12.3. MLAB Blocks in PR designs 1.12.4. Implementing Memories with Initialized Content 1.12.5. Initializing M20K Blocks with a Double PR Cycle
1.12.2. M20K RAM Blocks in PR Designs x
1.12.2.1. Limitations When Using Stratix V Production Devices
1. Design Planning for Partial Reconfiguration
A. Intel® Quartus® Prime Standard Edition User Guides

1.10. Programming Files for a Partial Reconfiguration Project

You must generate PR bitstream(s) based on the designs and send them to the control block for partial reconfiguration.

Compile the PR project, including the base revision and at least one reconfigurable revision before generating the PR bitstreams. The Intel® Quartus® Prime Programmer generates PR bitstreams. This generated bitstream can be sent to the PR ports on the control block for partial reconfiguration.

Figure 17. PR Project with Three Revisions

Consider a partial reconfiguration design that has three revisions and one PR region, a base revision with persona a, one PR revision with persona b, and a second PR revision with persona c.

When these individual revisions are compiled in the Intel® Quartus® Prime software, the assembler produces Masked SRAM Object Files (.msf) and the SRAM Object Files ( .sof) for each revision. The .sof files are created as before (for non-PR designs). Additionally, .msf files are created specifically for partial reconfiguration, one for each revision. The pr_region.mfsf file is the one of interest for generating the PR bitstream. It contains the mask bits for the PR region. Similarly, the static.msf file has the mask bits for the static region. The .sof files have the information on how to configure the static region as well as the corresponding PR region. The pr_region.msf file is used to mask out the static region so that the bitstream can be computed for the PR region. The default file name of the pr region .msf corresponds to the LogicLock region name, unless the name is not alphanumeric. In the case of a non-alphanumeric region name, the .msf file is named after the location of the lower left most coordinate of the region.

Note: Altera recommends naming all LogicLock regions to enhance documenting your design.
Figure 18. Generation of Partial-Masked SRAM Object Files (.pmsf)

You can convert files in the Convert Programming Files window or run the quartus_cpf -p command to process the pr_region.msf and .sof files to generate the Partial-Masked SRAM Object File (.pmsf).

The .msf file helps determine the PR region from each of the .sof files during the PR bitstream computation.

Once all the .pmsf files are created, process the PR bitstreams by running the quartus_cpf -o command to produce the raw binary .rbf files for reconfiguration.

If one wishes to partially reconfigure the PR region with persona a, use the a.rbf bitstream file, and so on for the other personas.

Figure 19. Generating PR Bitstreams

This figure shows how three bitstreams can be created to partially reconfigure the region with persona a, persona b, or persona c as desired.

In the Intel® Quartus® Prime software, the Convert Programming Files window supports the generation of the required programming bitstreams. When using the quartus_cpf from the command line, the following options for generating the programming files are read from an option text file, for example, option.txt.

  • If you want to use SCRUB mode, before generating the bitstreams create an option text file, with the following line:

    use_scrub=on

  • If you have initialized M20K blocks in the PR region (ROM/Initialized RAM), then add the following line in the option text file, before generating the bitstreams:

    write_block_memory_contents=on

  • If you want to compress the programming bitstream files, add the following line in the option text file. This option is available when converting base .sof to any supported programming file types, such as .rbf, .pof and JTAG Indirect Configuration File (. jic).

    bitstream_compression=on


Section Content
Generating Required Programming Files
Generate PR Programming Files with the Convert Programming Files Dialog Box

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