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1.1. Terminology
1.2. An Example of a Partial Reconfiguration Design
1.3. Partial Reconfiguration Modes
1.4. Partial Reconfiguration Design Flow
1.5. Freeze Logic for PR Regions
1.6. Implementation Details for Partial Reconfiguration
1.7. Example of a Partial Reconfiguration Design with an External Host
1.8. Example Partial Reconfiguration with an Internal Host
1.9. Partial Reconfiguration Project Management
1.10. Programming Files for a Partial Reconfiguration Project
1.11. On-Chip Debug for PR Designs
1.12. Partial Reconfiguration Known Limitations
1.13. Document Revision History
1.10.2.1. Generating a .pmsf File from a .msf and .sof Input File
1.10.2.2. Generating a .rbf File from a .pmsf Input File
1.10.2.3. Create a Merged .msf File from Multiple .msf Files
1.10.2.4. Generating a Merged .pmsf File from Multiple .pmsf Files
1.10.2.5. Enable Partial Reconfiguration Bitstream Decompression when Configuring Base Design SOF file in JTAG mode
1.10.2.6. Enable Bitstream Decryption Option
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1.4.3.3. Instantiating the PR Control Block and CRC Block in Verilog HDL
The following example instantiates a PR control block in Verilog HDL, inside your top-level project, Chip_Top:
module Chip_Top ( //User I/O signals (excluding PR related signals) .. .. //PR interface & configuration signals pr_request, pr_ready, pr_done, crc_error, dclk, pr_data, init_done ); //user I/O signal declaration .. .. //PR interface and configuration signals declaration input pr_request; output pr_ready; output pr_done; output crc_error; input dclk; input [15:0] pr_data; output init_done stratixv_prblock stratixv_prblock_inst ( .clk (dclk), .corectl (1'b0), .prrequest(pr_request), .data (pr_data), .error (pr_error), .ready (pr_ready), .done (pr_done) ); stratixv_crcblock stratixv_crcblock_inst ( .clk (clk), .shiftnld (1'b1), .crcerror (crc_error) ); endmodule
For more information on port connectivity for reading the Error Message Register (EMR), refer to the following application note.