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Ixiasoft
1.1.1. Determining Resources for Partial Reconfiguration
The functions in the periphery, such as GPIOs or I/O Registers, are controlled by I/O configuration bits and therefore cannot be partially reconfigured. Clock multiplexers for GCLK and QCLK are also not partially reconfigurable because they are controlled by I/O periphery bits.
These are the types of resource blocks in a Stratix V device.
Hardware Resource Block |
Reconfiguration Mode |
---|---|
Logic Block |
Partial Reconfiguration |
Digital Signal Processing |
Partial Reconfiguration |
Memory Block |
Partial Reconfiguration |
Transceivers |
Dynamic Reconfiguration ALTGX_Reconfig |
PLL |
Dynamic Reconfiguration ALTGX_Reconfig |
Core Routing |
Partial Reconfiguration |
Clock Networks |
Clock network sources cannot be changed, but a PLL driving a clock network can be dynamically reconfigured |
I/O Blocks and Other Periphery |
Not supported |
The transceivers and PLLs in Altera FPGAs can be reconfigured using dynamic reconfiguration. For more information on dynamic reconfiguration, refer to the Dynamic Reconfiguration in Stratix V Devices chapter in the Stratix V Handbook.