Visible to Intel only — GUID: mwh1409958558185
Ixiasoft
1.1. Terminology
1.2. An Example of a Partial Reconfiguration Design
1.3. Partial Reconfiguration Modes
1.4. Partial Reconfiguration Design Flow
1.5. Freeze Logic for PR Regions
1.6. Implementation Details for Partial Reconfiguration
1.7. Example of a Partial Reconfiguration Design with an External Host
1.8. Example Partial Reconfiguration with an Internal Host
1.9. Partial Reconfiguration Project Management
1.10. Programming Files for a Partial Reconfiguration Project
1.11. On-Chip Debug for PR Designs
1.12. Partial Reconfiguration Known Limitations
1.13. Document Revision History
1.10.2.1. Generating a .pmsf File from a .msf and .sof Input File
1.10.2.2. Generating a .rbf File from a .pmsf Input File
1.10.2.3. Create a Merged .msf File from Multiple .msf Files
1.10.2.4. Generating a Merged .pmsf File from Multiple .pmsf Files
1.10.2.5. Enable Partial Reconfiguration Bitstream Decompression when Configuring Base Design SOF file in JTAG mode
1.10.2.6. Enable Bitstream Decryption Option
Visible to Intel only — GUID: mwh1409958558185
Ixiasoft
1.7.1. Example of Using an External Host with Multiple Devices
You must design the external host to accommodate the arbitration scheme that is required for your system, as well as the partial reconfiguration interface requirement for each device.
Figure 15. Connecting Multiple FPGAs to an External Host
An example of an external host controlling multiple Stratix V devices on a board.