Visible to Intel only — GUID: mwh1409958546244
Ixiasoft
Visible to Intel only — GUID: mwh1409958546244
Ixiasoft
1.6.2. Partial Reconfiguration Pins
When using PR from pins, some of the I/O pins are dedicated for implementing partial reconfiguration functionality. If you perform partial reconfiguration from pins, then you must use the passive parallel with 16 data bits (FPPx16) configuration mode. All dual-purpose pins should also be specified to Use as regular I/O.
To enable partial reconfiguration from pins in the Intel® Quartus® Prime software, perform the following steps:
- From the Assignments menu, click Device, then click Device and Pin Options.
- In the Device and Pin Options dialog box, select Partial Reconfiguration in the Category list and turn on Enable PR pins from the Options list.
- Click Configuration in the Category list and select Passive Parallel x16 from the Configuration scheme list.
- Click Dual-Purpose Pins in the Category list and verify that all pins are set to Use as regular I/O rather than Use as input tri-stated.
- Click OK, or continue to modify other settings in the Device and Pin Options dialog box.
- Click OK.
Pin Name |
Pin Type |
Pin Description |
---|---|---|
PR_REQUEST | Input |
Dedicated input when Enable PR pins is turned on; otherwise, available as user I/O. Logic high on pin indicates the PR host is requesting partial reconfiguration. |
PR_READY | Output |
Dedicated output when Enable PR pins is turned on; otherwise, available as user I/O. Logic high on this pin indicates the Stratix V control block is ready to begin partial reconfiguration. |
PR_DONE | Output |
Dedicated output when Enable PR pins is turned on; otherwise, available as user I/O. Logic high on this pin indicates that partial reconfiguration is complete. |
PR_ERROR | Output |
Dedicated output when Enable PR pins is turned on; otherwise, available as user I/O. Logic high on this pin indicates the device has encountered an error during partial reconfiguration. |
DATA[15:0] | Input |
Dedicated input when Enable PR pins is turned on; otherwise available as user I/O. These pins provide connectivity for PR_DATA to transfer the PR bitstream to the PR Controller. |
DCLK | Bidirectional |
Dedicated input when Enable PR pins is turned on; PR_DATA is sent synchronous to this clock. |
For more information on different configuration modes for Stratix V devices, and specifically about FPPx16 mode, refer to the Configuration, Design Security, and Remote System Upgrades in Stratix V Devices chapter of the Stratix V Handbook.