Intel® Quartus® Prime Standard Edition User Guide: Partial Reconfiguration

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ID 683499
Date 9/24/2018
Public
Document Table of Contents
Document Table of Contents x
1. Design Planning for Partial Reconfiguration A. Intel® Quartus® Prime Standard Edition User Guides
1. Design Planning for Partial Reconfiguration x
1.1. Terminology 1.2. An Example of a Partial Reconfiguration Design 1.3. Partial Reconfiguration Modes 1.4. Partial Reconfiguration Design Flow 1.5. Freeze Logic for PR Regions 1.6. Implementation Details for Partial Reconfiguration 1.7. Example of a Partial Reconfiguration Design with an External Host 1.8. Example Partial Reconfiguration with an Internal Host 1.9. Partial Reconfiguration Project Management 1.10. Programming Files for a Partial Reconfiguration Project 1.11. On-Chip Debug for PR Designs 1.12. Partial Reconfiguration Known Limitations 1.13. Document Revision History
1.1. Terminology x
1.1.1. Determining Resources for Partial Reconfiguration
1.3. Partial Reconfiguration Modes x
1.3.1. SCRUB Mode 1.3.2. AND/OR Mode 1.3.3. Programming File Sizes for a Partial Reconfiguration Project
1.4. Partial Reconfiguration Design Flow x
1.4.1. Design Partitions for Partial Reconfiguration 1.4.2. Incremental Compilation Partitions for Partial Reconfiguration 1.4.3. Partial Reconfiguration Controller Instantiation in the Design 1.4.4. Wrapper Logic for PR Regions
1.4.3. Partial Reconfiguration Controller Instantiation in the Design x
1.4.3.1. Component Declaration of the PR Control Block and CRC Block in VHDL 1.4.3.2. Instantiating the PR Control Block and CRC Block in VHDL 1.4.3.3. Instantiating the PR Control Block and CRC Block in Verilog HDL
1.5. Freeze Logic for PR Regions x
1.5.1. Clocks and Other Global Signals for a PR Design 1.5.2. Floorplan Assignments for PR Designs
1.6. Implementation Details for Partial Reconfiguration x
1.6.1. Interface with the PR Control Block through a PR Host 1.6.2. Partial Reconfiguration Pins 1.6.3. PR Control Signals Interface 1.6.4. Reconfiguring a PR Region 1.6.5. Partial Reconfiguration Cycle Waveform
1.7. Example of a Partial Reconfiguration Design with an External Host x
1.7.1. Example of Using an External Host with Multiple Devices
1.9. Partial Reconfiguration Project Management x
1.9.1. Create Reconfigurable Revisions 1.9.2. Compiling Reconfigurable Revisions 1.9.3. Timing Closure for a Partial Reconfiguration Project 1.9.4. PR Bitstream Compression and Encryption ( Intel® Arria® 10 Designs)
1.10. Programming Files for a Partial Reconfiguration Project x
1.10.1. Generating Required Programming Files 1.10.2. Generate PR Programming Files with the Convert Programming Files Dialog Box
1.10.2. Generate PR Programming Files with the Convert Programming Files Dialog Box x
1.10.2.1. Generating a .pmsf File from a .msf and .sof Input File 1.10.2.2. Generating a .rbf File from a .pmsf Input File 1.10.2.3. Create a Merged .msf File from Multiple .msf Files 1.10.2.4. Generating a Merged .pmsf File from Multiple .pmsf Files 1.10.2.5. Enable Partial Reconfiguration Bitstream Decompression when Configuring Base Design SOF file in JTAG mode 1.10.2.6. Enable Bitstream Decryption Option
1.12. Partial Reconfiguration Known Limitations x
1.12.1. Memory Blocks Initialization Requirement for PR Designs 1.12.2. M20K RAM Blocks in PR Designs 1.12.3. MLAB Blocks in PR designs 1.12.4. Implementing Memories with Initialized Content 1.12.5. Initializing M20K Blocks with a Double PR Cycle
1.12.2. M20K RAM Blocks in PR Designs x
1.12.2.1. Limitations When Using Stratix V Production Devices
1. Design Planning for Partial Reconfiguration
A. Intel® Quartus® Prime Standard Edition User Guides

1.6.1. Interface with the PR Control Block through a PR Host

During partial reconfiguration, a PR bitstream stored outside the FPGA being partially reconfigured must be sent to the PR Control Block in the FPGA. This enables the control block to update the CRAM bits necessary to configure the PR region in the FPGA.
Two scenarios are possible, depending on whether the control logic to transfer the bitstream is located within the FPGA or outside the FPGA being reconfigured.
  • If the PR IP core is instantiated inside the FPGA being reconfigured, it is termed PR with an internal host; the Altera PR IP core helps you perform the transfer of the PR bitstream.
  • When the PR IP is instantiated outside the FPGA being reconfigured, it is termed as PR with an external host.

There is a well-defined interface and a specific protocol to transfer the PR bitstream from the external bitstream source to the PR control block. When you use the Altera PR IP core, the protocol requirements are automatically met by the IP.

It is also possible to write your own control logic, or use a Nios® processor to do this PR bitstream transfer. Note that when create your own control logic for the PR Host, you must make sure to meet the interface requirements described later in this chapter.

Figure 10. Managing Partial Reconfiguration with an Internal or External Host

The figure shows how these blocks should be connected to the PR control block (CB). In your system, you will have either the External Host or the Internal Host, but not both. The external host can be implemented by instantiating the PR IP core outside the FPGA being reconfigured, may be in another Altera FPGA, or processor/PC (PR over PCIe) , or can be implemented by user logic.

The PR mode is independent of the full chip programming mode. You can use any of the supported full chip configuration modes for configuring the full FPGA for your PR design.

If you are creating your own custom logic for implementing a PR internal host, you can use any interface to load the PR bitstream data to the FPGA; for example, from a serial or a parallel flash device; and then format the PR bitstream data to match the FPPx16 interface on the PR Control Block.

When using an external host, you must implement the control logic for managing system aspects of partial reconfiguration on an external device. To use the external host for your design, turn on the Enable PR Pins option in the Device and Pin Options dialog box in the Intel® Quartus® Prime software when you compile your design. If this setting is turned off, then you must use an internal host. Also, you must tie the corectl port on the PR control block instance in the top-level of the design to the appropriate level for the selected mode.

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