Visible to Intel only — GUID: mwh1409958590254
Ixiasoft
Visible to Intel only — GUID: mwh1409958590254
Ixiasoft
1.12.4. Implementing Memories with Initialized Content
If your Stratix V PR design implements ROMs, RAMs with initialization, or ROMs within the PR regions, using either M20K blocks or LUT-RAMs, then you must follow the following design guidelines to determine what is applicable in your case.
Mode |
Production Devices |
||
---|---|---|---|
AND/OR |
SCRUB |
||
LUT-RAM without initialization |
Suggested Method |
While design is running: Write ‘1’ to all locations before partial reconfiguration. At compile time: Explicitly initialize all memory locations in each new persona to ‘1’ via initialization file (.mif) Make sure no spurious write on PR entry 1 |
No special method required |
Without Suggested Method |
CRC Error | No special method required | |
LUT-RAM with initialization |
Suggested Method |
Not supported | Make sure no spurious write on PR exit 1 |
Without Suggested Method |
Incorrect results |
||
M20K without initialization |
Suggested Method |
No special method required | |
Without Suggested Method |
No special method required | ||
M20K with initialization |
Suggested Method |
Use double PR cycle 2 Make sure no spurious write on PR exit 1 |
No special method required |
Without Suggested Method |
Incorrect results | No special method required |
The circuit depends on an active- high clear signal from the static region. Before entering PR, freeze this signal in the same manner as all PR inputs. Your host control logic should de-assert the clear signal as the final step in the PR process.