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1.1. Terminology
1.2. An Example of a Partial Reconfiguration Design
1.3. Partial Reconfiguration Modes
1.4. Partial Reconfiguration Design Flow
1.5. Freeze Logic for PR Regions
1.6. Implementation Details for Partial Reconfiguration
1.7. Example of a Partial Reconfiguration Design with an External Host
1.8. Example Partial Reconfiguration with an Internal Host
1.9. Partial Reconfiguration Project Management
1.10. Programming Files for a Partial Reconfiguration Project
1.11. On-Chip Debug for PR Designs
1.12. Partial Reconfiguration Known Limitations
1.13. Document Revision History
1.10.2.1. Generating a .pmsf File from a .msf and .sof Input File
1.10.2.2. Generating a .rbf File from a .pmsf Input File
1.10.2.3. Create a Merged .msf File from Multiple .msf Files
1.10.2.4. Generating a Merged .pmsf File from Multiple .pmsf Files
1.10.2.5. Enable Partial Reconfiguration Bitstream Decompression when Configuring Base Design SOF file in JTAG mode
1.10.2.6. Enable Bitstream Decryption Option
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1.4.2. Incremental Compilation Partitions for Partial Reconfiguration
Use the following best practices guidelines when creating partitions for PR regions in your design:
- Register all partition boundaries; register all inputs and outputs of each partition when possible. This practice prevents any delay penalties on signals that cross partition boundaries and keeps each register-to-register timing path within one partition for optimization.
- Minimize the number of paths that cross partition boundaries.
- Minimize the timing-critical paths passing in or out of PR regions. If there are timing-critical paths that cross PR region boundaries, rework the PR regions to avoid these paths.
- The Intel® Quartus® Prime software can optimize some types of paths between design partitions for non-PR designs. However, for PR designs, such inter-partition paths are strictly not optimized.