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1.1. Terminology
1.2. An Example of a Partial Reconfiguration Design
1.3. Partial Reconfiguration Modes
1.4. Partial Reconfiguration Design Flow
1.5. Freeze Logic for PR Regions
1.6. Implementation Details for Partial Reconfiguration
1.7. Example of a Partial Reconfiguration Design with an External Host
1.8. Example Partial Reconfiguration with an Internal Host
1.9. Partial Reconfiguration Project Management
1.10. Programming Files for a Partial Reconfiguration Project
1.11. On-Chip Debug for PR Designs
1.12. Partial Reconfiguration Known Limitations
1.13. Document Revision History
1.10.2.1. Generating a .pmsf File from a .msf and .sof Input File
1.10.2.2. Generating a .rbf File from a .pmsf Input File
1.10.2.3. Create a Merged .msf File from Multiple .msf Files
1.10.2.4. Generating a Merged .pmsf File from Multiple .pmsf Files
1.10.2.5. Enable Partial Reconfiguration Bitstream Decompression when Configuring Base Design SOF file in JTAG mode
1.10.2.6. Enable Bitstream Decryption Option
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1.4.4. Wrapper Logic for PR Regions
Each persona of a PR region must implement the same input and output boundary ports. These ports act as the boundary between static and reconfigurable logic.
Implementing the same boundary ports ensures that all ports of a PR region remain stationary regardless of the underlying persona, so that the routing from the static logic does not change with different PR persona implementations.
Figure 8. Wire-LUTs at PR Region BoundaryThe Intel® Quartus® Prime software automatically instantiates a wire-LUT for each port of the PR region to lock down the same location for all instances of the PR persona.
If one persona of your PR region has a different number of ports than others, then you must create a wrapper so that the static region always communicates with this wrapper. In this wrapper, you can create dummy ports to ensure that all of the PR personas of a PR region have the same connection to the static region.
The sample code below each create two personas; persona_1 and persona_2 are different functions of one PR region. Note that one persona has a few dummy ports. The first example creates partial reconfiguration wrapper logic in Verilog HDL:
// Partial Reconfiguration Wrapper in Verilog HDL
module persona //this module is persona_1
(
input reset,
input [2:0] a,
input [2:0] b,
input [2:0] c,
output [3:0] p,
output [7:0] q
);
reg [3:0] p, q;
always@(a or b)
begin
p = a + b ;
end
always@(a or b or c or p)
begin
q = (p*a - b*c )
end
endmodule
module persona //this module is persona_2
(
input reset,
input [2:0] a,
input [2:0] b,
input [2:0] c, //never used in this persona
output [3:0] p,
output [7:0] q //never assigned in this persona
);
reg [3:0] p, q;
always@(a or b)
begin
p = a * b; // note q is not assigned value in this persona
end
endmodule
The following example creates partial reconfiguration wrapper logic in VHDL.
-- Partial Reconfiguration Wrapper in VHDL
-- this module is persona_1
entity persona is
port(
a:in STD_LOGIC_VECTOR (2 downto 0);
b:in STD_LOGIC_VECTOR (2 downto 0);
c:in STD_LOGIC_VECTOR (2 downto 0);
p: out STD_LOGIC_VECTOR (3 downto 0);
q: out STD_LOGIC_VECTOR (7 downto 0)
);
end persona;
architecture synth of persona is
begin
process(a,b)
begin
p <= a + b;
end process;
process (a, b, c, p)
begin
q <= (p*a - b*c);
end process;
end synth;
-- this module is persona_2
entity persona is
port(
a:in STD_LOGIC_VECTOR (2 downto 0);
b:in STD_LOGIC_VECTOR (2 downto 0);
c:in STD_LOGIC_VECTOR (2 downto 0); --never used in this persona
p:out STD_LOGIC_VECTOR (3 downto 0);
q:out STD_LOGIC_VECTOR (7 downto 0) --never used in this persona
);
end persona_2;
architecture synth of persona_2 is
begin
process(a, b)
begin
p <= a *b; --note q is not assigned a value in this persona
end process;
end synth;