JESD204B Intel® FPGA IP User Guide

Download PDF
ID 683442
Date 12/16/2024
Public
Document Table of Contents
Document Table of Contents x
1. JESD204B IP Quick Reference 2. About the JESD204B Intel® FPGA IP 3. Getting Started 4. JESD204B IP Functional Description 5. JESD204B IP Deterministic Latency Implementation Guidelines 6. JESD204B IP Debug Guidelines 7. JESD204B Intel® FPGA IP User Guide Archives 8. Document Revision History for the JESD204B Intel® FPGA IP User Guide
2. About the JESD204B Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. Datapath Modes 2.4. IP Variation 2.5. JESD204B IP Configuration 2.6. Channel Bonding 2.7. Performance and Resource Utilization
2.5. JESD204B IP Configuration x
2.5.1. Run-Time Configuration
3. Getting Started x
3.1. Introduction to Intel® FPGA IP Cores 3.2. Installing and Licensing Intel® FPGA IP Cores 3.3. Intel® FPGA IP Evaluation Mode 3.4. Upgrading IP Cores 3.5. IP Catalog and Parameter Editor 3.6. Design Walkthrough 3.7. JESD204B Design Examples 3.8. JESD204B IP Design Considerations 3.9. JESD204B Intel® FPGA IP Parameters 3.10. JESD204B IP Component Files 3.11. JESD204B IP Testbench
3.6. Design Walkthrough x
3.6.1. Creating a New Quartus® Prime Project 3.6.2. Parameterizing and Generating the IP 3.6.3. Compiling the JESD204B IP Core Design 3.6.4. Programming an FPGA Device
3.8. JESD204B IP Design Considerations x
3.8.1. Integrating the JESD204B IP in Platform Designer 3.8.2. Pin Assignments 3.8.3. Adding External Transceiver PLLs 3.8.4. Timing Constraints For Input Clocks
3.11. JESD204B IP Testbench x
3.11.1. Generating and Simulating the IP Testbench 3.11.2. Testbench Simulation Flow
3.11.1. Generating and Simulating the IP Testbench x
3.11.1.1. Generating the Testbench Simulation Model 3.11.1.2. Simulating the IP Testbench
4. JESD204B IP Functional Description x
4.1. Transmitter 4.2. Receiver 4.3. Operation 4.4. Clocking Scheme 4.5. Reset Scheme 4.6. Signals 4.7. Registers
4.1. Transmitter x
4.1.1. TX Data Link Layer 4.1.2. TX PHY Layer
4.1.1. TX Data Link Layer x
4.1.1.1. TX CGS 4.1.1.2. TX ILAS 4.1.1.3. User Data Phase
4.2. Receiver x
4.2.1. RX Data Link Layer 4.2.2. RX PHY Layer
4.2.1. RX Data Link Layer x
4.2.1.1. RX CGS 4.2.1.2. Frame Synchronization 4.2.1.3. Frame Alignment 4.2.1.4. Lane Alignment 4.2.1.5. ILAS Data 4.2.1.6. Initial Lane Synchronization
4.3. Operation x
4.3.1. Operating Modes 4.3.2. Scrambler/Descrambler 4.3.3. SYNC_N Signal 4.3.4. Link Reinitialization 4.3.5. Link Startup Sequence 4.3.6. Error Reporting Through SYNC_N Signal
4.3.1. Operating Modes x
4.3.1.1. Subclass 0 Operating Mode 4.3.1.2. Subclass 1 Operating Mode 4.3.1.3. Subclass 2 Operating Mode
4.4. Clocking Scheme x
4.4.1. Device Clock 4.4.2. Link Clock 4.4.3. Local MultiFrame Clock 4.4.4. Clock Correlation 4.4.5. Transceiver Calibration Clock Source
4.5. Reset Scheme x
4.5.1. Reset Sequence 4.5.2. ADC–FPGA Subsystem Reset Sequence 4.5.3. FPGA–DAC Subsystem Reset Sequence
4.6. Signals x
4.6.1. Transmitter Signals 4.6.2. Receiver Signals
4.7. Registers x
4.7.1. Register Access Type Convention 4.7.2. Transmitter Registers 4.7.3. Receiver Registers
5. JESD204B IP Deterministic Latency Implementation Guidelines x
5.1. SYSREF Guidelines 5.2. Constraining Incoming SYSREF Signal 5.3. Programmable RBD Offset 5.4. Programmable LMFC Offset 5.5. Maintaining Deterministic Latency during Link Reinitialization
6. JESD204B IP Debug Guidelines x
6.1. Clocking Scheme 6.2. JESD204B Parameters 6.3. SPI Programming 6.4. Converter and FPGA Operating Conditions 6.5. Signal Polarity and FPGA Pin Assignment 6.6. Creating a Signal Tap Debug File to Match Your Design Hierarchy 6.7. Debugging JESD204B Link Using System Console
6.6. Creating a Signal Tap Debug File to Match Your Design Hierarchy x
6.6.1. Removing Irrelevant Signals and Adding E-Tile PHY Signals
1. JESD204B IP Quick Reference
2. About the JESD204B Intel® FPGA IP
3. Getting Started
4. JESD204B IP Functional Description
5. JESD204B IP Deterministic Latency Implementation Guidelines
6. JESD204B IP Debug Guidelines
7. JESD204B Intel® FPGA IP User Guide Archives
8. Document Revision History for the JESD204B Intel® FPGA IP User Guide

4.5. Reset Scheme

All resets in the JESD204B IP are synchronous reset signals and should be asserted and deasserted synchronously.
Note: Ensure that the resets are synchronized to the respective clocks for reset assertion and deassertion.
Table 24.   JESD204B IP Resets
Reset Signal Associated Clock Description

txlink_rst_n

rxlink_rst_n

TX/RX Link Clock Active low reset. Intel® recommends that you:
  • Assert the txlink_rst_n/rxlink_rst_n and txframe_rst_n /rxframe_rst_n signals when the transceiver is in reset.
  • Deassert the txlink_rst_n and txframe_rst_n signals after the Intel® FPGA PLL IP is locked and the tx_ready[] signal from the Transceiver Reset Controller is asserted.
  • Deassert the rxlink_rst_n and rxframe_rst_n signals after the Transceiver CDR rx_islockedtodata[] signal and rx_ready[] signal from the Transceiver Reset Controller are asserted.

The txlink_rst_n/rxlink_rst_n and txframe_rst_n /rxframe_rst_n signals can be deasserted at the same time. These resets can only be deasserted after you configure the CSR registers.

txframe_rst_n

rxframe_rst_n

TX/RX Frame Clock Active low reset controlled by the clock and reset unit. If the TX/RX link clock and the TX/RX frame clock has the same frequency, both can share the same reset.

tx_analogreset[L-1:0]

rx_analogreset[L-1:0]

Transceiver Native PHY Analog Reset Active high reset controlled by the transceiver reset controller. This signal resets the TX/RX PMA.
The link clock, frame clock, and AVS clock reset signals (txlink_rst_n/rxlink_rst_n, txframe_rst_n/rxframe_rst_n and jesd204_tx_avs_rst_n/jesd204_rx_avs_rst_n) can only be deasserted after the transceiver comes out of reset. 28
Note: This signal is not applicable for Agilex™ 7 and Stratix® 10 E-tile devices.

tx_analogreset_stat[L-1:0]

rx_analogreset_stat[L-1:0]

Transceiver Native PHY Analog Reset TX PMA analog reset status port connected to the transceiver reset controller. 29
Note: This signal is applicable only for Stratix® 10 L-tile and H-tile devices.

tx_digitalreset[L-1:0]

rx_digitalreset[L-1:0]

Transceiver Native PHY Digital Reset Active high reset controlled by the transceiver reset controller. This signal resets the TX/RX PCS.
The link clock, frame clock, and AVS clock reset signals (txlink_rst_n/rxlink_rst_n, txframe_rst_n/rxframe_rst_n and jesd204_tx_avs_rst_n/jesd204_rx_avs_rst_n) can only be deasserted after the transceiver comes out of reset. 28
Note: This signal is not applicable for Agilex™ 7 and Stratix® 10 E-tile devices.

tx_digitalreset_stat[L-1:0]

rx_digitalreset_stat[L-1:0]

Transceiver Native PHY Digital Reset TX PCS digital reset status port connected to the transceiver reset controller.29
Note: This signal is applicable only for Stratix® 10 L-tile and H-tile devices.

jesd204_tx_avs_rst_n

jesd204_rx_avs_rst_n

TX/RX AVS (CSR) Clock Active low reset controlled by the clock and reset unit. Typically, both signals can be deasserted after the core PLL and transceiver PLL are locked and out of reset. If you want to dynamically modify the LMF at run-time, you can program the CSRs after AVS reset is deasserted. This phase is referred to as the configuration phase.

After the configuration phase is complete, then only the txlink_rst_n/rxlink_rst_n and txframe_rst_n/rxframe_rst_n signals can be deasserted.


Section Content
Reset Sequence
ADC–FPGA Subsystem Reset Sequence
FPGA–DAC Subsystem Reset Sequence

Related Information
28 Refer to the respective Transceiver PHY IP User Guides for the timing diagram of the tx_analogreset, rx_analogreset, tx_digitalreset, and rx_digitalreset signals.
29 Refer to the Stratix® 10 L- and H-tile Transceiver PHY IP User Guide for the timing diagram of the tx_analogreset_stat, rx_analogreset_stat, tx_digitalreset_stat, and rx_digitalreset_stat signals.
Level Two Title