JESD204B Intel® FPGA IP User Guide

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ID 683442
Date 7/19/2024
Public
Document Table of Contents
Document Table of Contents x
1. JESD204B IP Quick Reference 2. About the JESD204B Intel® FPGA IP 3. Getting Started 4. JESD204B IP Functional Description 5. JESD204B IP Deterministic Latency Implementation Guidelines 6. JESD204B IP Debug Guidelines 7. JESD204B Intel® FPGA IP User Guide Archives 8. Document Revision History for the JESD204B Intel® FPGA IP User Guide
2. About the JESD204B Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. Datapath Modes 2.4. IP Variation 2.5. JESD204B IP Configuration 2.6. Channel Bonding 2.7. Performance and Resource Utilization
2.5. JESD204B IP Configuration x
2.5.1. Run-Time Configuration
3. Getting Started x
3.1. Introduction to Intel® FPGA IP Cores 3.2. Installing and Licensing Intel® FPGA IP Cores 3.3. Intel® FPGA IP Evaluation Mode 3.4. Upgrading IP Cores 3.5. IP Catalog and Parameter Editor 3.6. Design Walkthrough 3.7. JESD204B Design Examples 3.8. JESD204B IP Design Considerations 3.9. JESD204B Intel® FPGA IP Parameters 3.10. JESD204B IP Component Files 3.11. JESD204B IP Testbench
3.6. Design Walkthrough x
3.6.1. Creating a New Quartus® Prime Project 3.6.2. Parameterizing and Generating the IP 3.6.3. Compiling the JESD204B IP Core Design 3.6.4. Programming an FPGA Device
3.8. JESD204B IP Design Considerations x
3.8.1. Integrating the JESD204B IP in Platform Designer 3.8.2. Pin Assignments 3.8.3. Adding External Transceiver PLLs 3.8.4. Timing Constraints For Input Clocks
3.11. JESD204B IP Testbench x
3.11.1. Generating and Simulating the IP Testbench 3.11.2. Testbench Simulation Flow
3.11.1. Generating and Simulating the IP Testbench x
3.11.1.1. Generating the Testbench Simulation Model 3.11.1.2. Simulating the IP Testbench
4. JESD204B IP Functional Description x
4.1. Transmitter 4.2. Receiver 4.3. Operation 4.4. Clocking Scheme 4.5. Reset Scheme 4.6. Signals 4.7. Registers
4.1. Transmitter x
4.1.1. TX Data Link Layer 4.1.2. TX PHY Layer
4.1.1. TX Data Link Layer x
4.1.1.1. TX CGS 4.1.1.2. TX ILAS 4.1.1.3. User Data Phase
4.2. Receiver x
4.2.1. RX Data Link Layer 4.2.2. RX PHY Layer
4.2.1. RX Data Link Layer x
4.2.1.1. RX CGS 4.2.1.2. Frame Synchronization 4.2.1.3. Frame Alignment 4.2.1.4. Lane Alignment 4.2.1.5. ILAS Data 4.2.1.6. Initial Lane Synchronization
4.3. Operation x
4.3.1. Operating Modes 4.3.2. Scrambler/Descrambler 4.3.3. SYNC_N Signal 4.3.4. Link Reinitialization 4.3.5. Link Startup Sequence 4.3.6. Error Reporting Through SYNC_N Signal
4.3.1. Operating Modes x
4.3.1.1. Subclass 0 Operating Mode 4.3.1.2. Subclass 1 Operating Mode 4.3.1.3. Subclass 2 Operating Mode
4.4. Clocking Scheme x
4.4.1. Device Clock 4.4.2. Link Clock 4.4.3. Local MultiFrame Clock 4.4.4. Clock Correlation 4.4.5. Transceiver Calibration Clock Source
4.5. Reset Scheme x
4.5.1. Reset Sequence 4.5.2. ADC–FPGA Subsystem Reset Sequence 4.5.3. FPGA–DAC Subsystem Reset Sequence
4.6. Signals x
4.6.1. Transmitter Signals 4.6.2. Receiver Signals
4.7. Registers x
4.7.1. Register Access Type Convention 4.7.2. Transmitter Registers 4.7.3. Receiver Registers
5. JESD204B IP Deterministic Latency Implementation Guidelines x
5.1. SYSREF Guidelines 5.2. Constraining Incoming SYSREF Signal 5.3. Programmable RBD Offset 5.4. Programmable LMFC Offset 5.5. Maintaining Deterministic Latency during Link Reinitialization
6. JESD204B IP Debug Guidelines x
6.1. Clocking Scheme 6.2. JESD204B Parameters 6.3. SPI Programming 6.4. Converter and FPGA Operating Conditions 6.5. Signal Polarity and FPGA Pin Assignment 6.6. Creating a Signal Tap Debug File to Match Your Design Hierarchy 6.7. Debugging JESD204B Link Using System Console
6.6. Creating a Signal Tap Debug File to Match Your Design Hierarchy x
6.6.1. Removing Irrelevant Signals and Adding E-Tile PHY Signals
1. JESD204B IP Quick Reference
2. About the JESD204B Intel® FPGA IP
3. Getting Started
4. JESD204B IP Functional Description
5. JESD204B IP Deterministic Latency Implementation Guidelines
6. JESD204B IP Debug Guidelines
7. JESD204B Intel® FPGA IP User Guide Archives
8. Document Revision History for the JESD204B Intel® FPGA IP User Guide

4.5.3. FPGA–DAC Subsystem Reset Sequence

Figure 23. FPGA–DAC Subsystem Reset Sequence Timing Diagram

The recommended FPGA – DAC subsystem bring-up sequence:

  1. Provide a free-running and stable reference clock to the converter and FPGA in the JESD204B subsystem. The reference clock for the converter is the device clock. Intel® recommends four reference clocks for the FPGA.
    1. The first reference clock is the calibration clock for the transceiver.
      • For Stratix® 10 devices, this is the clock at the OSC_CLK_1 pin for the calibration engine.
      • For Arria® 10 and Cyclone® 10 GX devices, this is the clock at the CLKUSR pin for the calibration engine.
      • For Arria® V, Cyclone® V, and Stratix® V devices, this is the clock for the transceiver reconfiguration controller.
    2. The second reference clock is the management clock for the transceiver reconfiguration interface and the JESD204B IP core Avalon® memory-mapped interface.
      • If the dynamic reconfiguration option is enabled for Arria® 10, Cyclone® 10 GX, and Stratix® 10 devices, this reference clock is connected to the reconfig_clk input port of the JESD204B IP core.
    3. The third reference clock is the transceiver reference clock.
      • For Stratix® 10, you must provide the reference clock at the transceiver dedicated reference clock input pin.
      • For Arria® 10, Cyclone® 10 GX, Arria® V, Cyclone® V, and Stratix® V, this clock is also used as the reference clock for the core PLL (IOPLL Intel® FPGA IP core for Arria® 10 and Cyclone® 10 GX; and PLL Intel® FPGA IP core for Arria® V, Cyclone® V, and Stratix® V devices) if you share the device clock and the transceiver reference clock (refer to Device Clock).
    4. The fourth reference clock is the core PLL reference clock (device clock).
      • For Stratix® 10, you must provide the reference clock at the dedicated reference clock input pin at the IO bank.
      • For Arria® 10, Cyclone® 10 GX, Arria® V, Cyclone® V, and Stratix® V, this is the reference clock for the core PLL (IOPLL Intel® FPGA IP core for Arria® 10 and Cyclone® 10 GX devices; and PLL Intel® FPGA IP core for Arria® V, Cyclone® V, and Stratix® V devices) if you do not share the device clock and the transceiver reference clock (refer to Device Clock).
  2. Configure the FPGA. Hold the TX transceiver PLL and channel in reset.
    • For Arria® 10 and Cyclone® 10 GX devices, if the reference clock is not available for the transceiver PLL before the FPGA is configured, you need to hold the transceiver PLL and channels in reset and perform user calibration for the transceiver PLL and TX channels after the reference clock is stable. For more information about user calibration for the transceiver PLL and channels, refer to the Calibration chapter in the Arria® 10 or Cyclone® 10 GX Transceiver PHY User Guides.
  3. Ensure that the FPGA device clock core PLL is locked to the reference clock.
  4. Deassert the FPGA TX transceiver PLL and channel reset. Do this by deasserting the reset input pin of the Transceiver PHY Reset Controller.
  5. Ensure that the FPGA transceiver PLL is locked to the reference clock.
  6. Once the TX transceiver PLL and channel are out of reset (the tx_ready signal from the Transceiver PHY Reset Controller is asserted), deassert the Avalon® memory-mapped interface reset for the IP core. At the configuration phase, the subsystem can program the JESD204B IP core if the default IP core register settings need to change.
  7. Deassert both the link reset for the IP core and ensure transport layer is out-of-reset.
  8. The TX IP core streams /K/ characters to the DAC after TX link reset is deasserted.
  9. Program the DAC through its SPI interface.
  10. For subclass 1, the clock generator only starts to generate SYSREF pulses after two link clock cycles since TX link reset deassertion. The TX-DAC link initializes when the first rising edge of SYSREF is detected.
  11. For subclass 0, the link initializes after the DAC is programmed and the TX link reset is deasserted.
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