JESD204B Intel® FPGA IP User Guide

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ID 683442
Date 12/16/2024
Public
Document Table of Contents
Document Table of Contents x
1. JESD204B IP Quick Reference 2. About the JESD204B Intel® FPGA IP 3. Getting Started 4. JESD204B IP Functional Description 5. JESD204B IP Deterministic Latency Implementation Guidelines 6. JESD204B IP Debug Guidelines 7. JESD204B Intel® FPGA IP User Guide Archives 8. Document Revision History for the JESD204B Intel® FPGA IP User Guide
2. About the JESD204B Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. Datapath Modes 2.4. IP Variation 2.5. JESD204B IP Configuration 2.6. Channel Bonding 2.7. Performance and Resource Utilization
2.5. JESD204B IP Configuration x
2.5.1. Run-Time Configuration
3. Getting Started x
3.1. Introduction to Intel® FPGA IP Cores 3.2. Installing and Licensing Intel® FPGA IP Cores 3.3. Intel® FPGA IP Evaluation Mode 3.4. Upgrading IP Cores 3.5. IP Catalog and Parameter Editor 3.6. Design Walkthrough 3.7. JESD204B Design Examples 3.8. JESD204B IP Design Considerations 3.9. JESD204B Intel® FPGA IP Parameters 3.10. JESD204B IP Component Files 3.11. JESD204B IP Testbench
3.6. Design Walkthrough x
3.6.1. Creating a New Quartus® Prime Project 3.6.2. Parameterizing and Generating the IP 3.6.3. Compiling the JESD204B IP Core Design 3.6.4. Programming an FPGA Device
3.8. JESD204B IP Design Considerations x
3.8.1. Integrating the JESD204B IP in Platform Designer 3.8.2. Pin Assignments 3.8.3. Adding External Transceiver PLLs 3.8.4. Timing Constraints For Input Clocks
3.11. JESD204B IP Testbench x
3.11.1. Generating and Simulating the IP Testbench 3.11.2. Testbench Simulation Flow
3.11.1. Generating and Simulating the IP Testbench x
3.11.1.1. Generating the Testbench Simulation Model 3.11.1.2. Simulating the IP Testbench
4. JESD204B IP Functional Description x
4.1. Transmitter 4.2. Receiver 4.3. Operation 4.4. Clocking Scheme 4.5. Reset Scheme 4.6. Signals 4.7. Registers
4.1. Transmitter x
4.1.1. TX Data Link Layer 4.1.2. TX PHY Layer
4.1.1. TX Data Link Layer x
4.1.1.1. TX CGS 4.1.1.2. TX ILAS 4.1.1.3. User Data Phase
4.2. Receiver x
4.2.1. RX Data Link Layer 4.2.2. RX PHY Layer
4.2.1. RX Data Link Layer x
4.2.1.1. RX CGS 4.2.1.2. Frame Synchronization 4.2.1.3. Frame Alignment 4.2.1.4. Lane Alignment 4.2.1.5. ILAS Data 4.2.1.6. Initial Lane Synchronization
4.3. Operation x
4.3.1. Operating Modes 4.3.2. Scrambler/Descrambler 4.3.3. SYNC_N Signal 4.3.4. Link Reinitialization 4.3.5. Link Startup Sequence 4.3.6. Error Reporting Through SYNC_N Signal
4.3.1. Operating Modes x
4.3.1.1. Subclass 0 Operating Mode 4.3.1.2. Subclass 1 Operating Mode 4.3.1.3. Subclass 2 Operating Mode
4.4. Clocking Scheme x
4.4.1. Device Clock 4.4.2. Link Clock 4.4.3. Local MultiFrame Clock 4.4.4. Clock Correlation 4.4.5. Transceiver Calibration Clock Source
4.5. Reset Scheme x
4.5.1. Reset Sequence 4.5.2. ADC–FPGA Subsystem Reset Sequence 4.5.3. FPGA–DAC Subsystem Reset Sequence
4.6. Signals x
4.6.1. Transmitter Signals 4.6.2. Receiver Signals
4.7. Registers x
4.7.1. Register Access Type Convention 4.7.2. Transmitter Registers 4.7.3. Receiver Registers
5. JESD204B IP Deterministic Latency Implementation Guidelines x
5.1. SYSREF Guidelines 5.2. Constraining Incoming SYSREF Signal 5.3. Programmable RBD Offset 5.4. Programmable LMFC Offset 5.5. Maintaining Deterministic Latency during Link Reinitialization
6. JESD204B IP Debug Guidelines x
6.1. Clocking Scheme 6.2. JESD204B Parameters 6.3. SPI Programming 6.4. Converter and FPGA Operating Conditions 6.5. Signal Polarity and FPGA Pin Assignment 6.6. Creating a Signal Tap Debug File to Match Your Design Hierarchy 6.7. Debugging JESD204B Link Using System Console
6.6. Creating a Signal Tap Debug File to Match Your Design Hierarchy x
6.6.1. Removing Irrelevant Signals and Adding E-Tile PHY Signals
1. JESD204B IP Quick Reference
2. About the JESD204B Intel® FPGA IP
3. Getting Started
4. JESD204B IP Functional Description
5. JESD204B IP Deterministic Latency Implementation Guidelines
6. JESD204B IP Debug Guidelines
7. JESD204B Intel® FPGA IP User Guide Archives
8. Document Revision History for the JESD204B Intel® FPGA IP User Guide

6.6. Creating a Signal Tap Debug File to Match Your Design Hierarchy

The Signal Tap and system console are very useful tools in debugging the JESD204B link related issues. The Signal Tap provides a dynamic view of signals.

For Arria® 10, Cyclone® 10 GX, and Stratix® 10 devices, the Quartus® Prime software generates two files, build_stp.tcl and <ip_core_name>.xml. You can use these files to generate a Signal Tap file with probe points matching your design hierarchy.

The Quartus® Prime software stores these files in the <debug stp directory>. The <debug stp directory> is defined based on JESD204B wrapper and data path.

File Directory
JESD204B Wrapper Data Path Debug stp directory
Both Base and PHY Transmitter/Duplex <ip_variant_name>/altera_jesd204_tx_mlpcs_<Quartus_version>/synth/debug/stp
Receiver <ip_variant_name>/altera_jesd204_rx_mlpcs_<Quartus_version>/synth/debug/stp
Base only Transmitter <ip_variant_name>/altera_jesd204_tx_<Quartus_version>/synth/debug/stp
Receiver <ip_variant_name>/altera_jesd204_rx_<Quartus_version>/synth/debug/stp
Synthesize your design by running Analysis and Synthesis in the Quartus® Prime software.
  1. Run analysis and synthesis.
  2. Then open the Tcl console by clicking View > Utility Windows > Tcl Console.
  3. Navigate to the <debug stp directory> as shown in File Directory.
  4. Type the following command in the Tcl console: 
    source build_stp.tcl
  5. To generate the STP file, type the following command: 
    main -stp_file <stp file name>.stp -xml_file 
<xml_file name>.xml -mode build
    The <stp file name>.stp file is generated in the <debug stp directory>.
  6. The software generation script may not assign the Signal Tap acquisition clock in the <stp file name>.stp file. Consequently, the Quartus® Prime software automatically creates a clock pin (auto_stp_external_clock) for each instance. To assign an acquisition clock for the generated STP file, Intel® recommends that you perform the following assignments:
    JESD204B Duplex & Simplex (Both Base & PHY) or (PHY only) IP core:-
    • For rx_link instance, assign the rxlink_clk signal.
    • For tx_link instance, assign the txlink_clk signal.
    • For all supported devices, except Stratix® 10 E-tile devices:

      For rx_phy and tx_phy instances, assign the input clock of the transceiver reset controller.

    • For Stratix® 10 E-tile devices:
      For rx_phy and tx_phy instances, assign rxphy_clk[0] and txphy_clk[0] as the acquisition clock. Then, add the following set_false_path constraint in the SDC script. 
      set_false_path -from 
      <instance_name>|inst_phy|inst_xcvr|*counter_*x_ready|r_reset -to 
      auto_fab*sld_signaltap_inst*
    Note: The PHY signals are different for Stratix® 10 E-tile devices. Remove the irrelevant signals and add the Stratix® 10 E-tile device PHY signals into the Signal Tap Logic Analyzer. Refer to Removing Irrelevant Signals and Adding E-Tile PHY Signals.
    JESD204B Simplex (Base only) IP core:-
    • For rx_link instance, assign the rxlink_clk signal.
    • For tx_link instance, assign the txlink_clk signal.
    Note: The GUI parameter editor allows you to choose the appropriate instance for each IP core name if your design contains more than one JESD204B instances. For simplex core, you need to choose the RX instance followed by TX instance to generate the proper STP file.
  7. Click Save to save the modified STP. A dialog box pops up with a message "Do you want to enable Signal Tap File "<stp file name>" for the current project?". Click Yes. Then, compile your design.
  8. To program the FPGA, click Tools > Programmer.
  9. Open the generated STP file again if it has closed after step 6.
  10. To observe the state of your IP core, click Run Analysis in the Signal Tap Logic Analyzer.
    You may see signals or Signal Tap instances that are red, indicating they are not available in your design. In most cases, you can safely ignore these signals and instances because the software generates wider buses and certain instances that your design does not include.

Section Content
Removing Irrelevant Signals and Adding E-Tile PHY Signals

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